On 11/07/2016 12:33, Yang Zhang wrote:
> On 2016/7/11 17:17, Paolo Bonzini wrote:
>> On 11/07/2016 10:56, Yang Zhang wrote:
>>> On 2016/7/11 15:44, Paolo Bonzini wrote:
On 11/07/2016 08:06, Yang Zhang wrote:
If interrupt remapping is on, KVM_CAP_X2APIC_API is needed even with 8
On 11/07/2016 12:33, Yang Zhang wrote:
> On 2016/7/11 17:17, Paolo Bonzini wrote:
>> On 11/07/2016 10:56, Yang Zhang wrote:
>>> On 2016/7/11 15:44, Paolo Bonzini wrote:
On 11/07/2016 08:06, Yang Zhang wrote:
If interrupt remapping is on, KVM_CAP_X2APIC_API is needed even with 8
On 2016/7/11 17:17, Paolo Bonzini wrote:
On 11/07/2016 10:56, Yang Zhang wrote:
On 2016/7/11 15:44, Paolo Bonzini wrote:
On 11/07/2016 08:06, Yang Zhang wrote:
Changes to MSI addresses follow the format used by interrupt remapping
unit.
The upper address word, that used to be 0, contains
On 2016/7/11 17:17, Paolo Bonzini wrote:
On 11/07/2016 10:56, Yang Zhang wrote:
On 2016/7/11 15:44, Paolo Bonzini wrote:
On 11/07/2016 08:06, Yang Zhang wrote:
Changes to MSI addresses follow the format used by interrupt remapping
unit.
The upper address word, that used to be 0, contains
On 11/07/2016 10:56, Yang Zhang wrote:
> On 2016/7/11 15:44, Paolo Bonzini wrote:
>>
>>
>> On 11/07/2016 08:06, Yang Zhang wrote:
Changes to MSI addresses follow the format used by interrupt remapping
unit.
The upper address word, that used to be 0, contains upper 24 bits of
On 11/07/2016 10:56, Yang Zhang wrote:
> On 2016/7/11 15:44, Paolo Bonzini wrote:
>>
>>
>> On 11/07/2016 08:06, Yang Zhang wrote:
Changes to MSI addresses follow the format used by interrupt remapping
unit.
The upper address word, that used to be 0, contains upper 24 bits of
On 2016/7/11 15:44, Paolo Bonzini wrote:
On 11/07/2016 08:06, Yang Zhang wrote:
Changes to MSI addresses follow the format used by interrupt remapping
unit.
The upper address word, that used to be 0, contains upper 24 bits of
the LAPIC
address in its upper 24 bits. Lower 8 bits are reserved
On 2016/7/11 15:44, Paolo Bonzini wrote:
On 11/07/2016 08:06, Yang Zhang wrote:
Changes to MSI addresses follow the format used by interrupt remapping
unit.
The upper address word, that used to be 0, contains upper 24 bits of
the LAPIC
address in its upper 24 bits. Lower 8 bits are reserved
On 11/07/2016 08:06, Yang Zhang wrote:
>> Changes to MSI addresses follow the format used by interrupt remapping
>> unit.
>> The upper address word, that used to be 0, contains upper 24 bits of
>> the LAPIC
>> address in its upper 24 bits. Lower 8 bits are reserved as 0.
>> Using the upper
On 11/07/2016 08:06, Yang Zhang wrote:
>> Changes to MSI addresses follow the format used by interrupt remapping
>> unit.
>> The upper address word, that used to be 0, contains upper 24 bits of
>> the LAPIC
>> address in its upper 24 bits. Lower 8 bits are reserved as 0.
>> Using the upper
On 2016/7/8 1:15, Radim Krčmář wrote:
KVM_CAP_X2APIC_API can be enabled to extend APIC ID in get/set ioctl and MSI
addresses to 32 bits. Both are needed to support x2APIC.
The capability has to be toggleable and disabled by default, because get/set
ioctl shifted and truncated APIC ID to 8 bits
On 2016/7/8 1:15, Radim Krčmář wrote:
KVM_CAP_X2APIC_API can be enabled to extend APIC ID in get/set ioctl and MSI
addresses to 32 bits. Both are needed to support x2APIC.
The capability has to be toggleable and disabled by default, because get/set
ioctl shifted and truncated APIC ID to 8 bits
KVM_CAP_X2APIC_API can be enabled to extend APIC ID in get/set ioctl and MSI
addresses to 32 bits. Both are needed to support x2APIC.
The capability has to be toggleable and disabled by default, because get/set
ioctl shifted and truncated APIC ID to 8 bits by using a non-standard protocol
KVM_CAP_X2APIC_API can be enabled to extend APIC ID in get/set ioctl and MSI
addresses to 32 bits. Both are needed to support x2APIC.
The capability has to be toggleable and disabled by default, because get/set
ioctl shifted and truncated APIC ID to 8 bits by using a non-standard protocol
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