Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
On Wed, Mar 11, 2015 at 03:44:39PM +, Sudeep Holla wrote: > It looks fine to me except one unwanted/incorrect line in the commit log as > mentioned below. I gave it a spin on my i7 box and it works. > Thanks for the fix up. Thanks for testing. > After testing this patch, I think I had misunderstood before and it's > not populated on Intel processors, so you can drop the line above. Done. :) -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. -- -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
Hi Boris, On 11/03/15 13:36, Borislav Petkov wrote: On Tue, Mar 10, 2015 at 02:35:12PM +, Sudeep Holla wrote: My initial assumption was that it will be NULL for Intel processors and hence I assigned cacheinfo->priv to nb pointer unconditionally. So I don't have any strong opinion here. Right, we need the NB descriptor on AMD to do L3-specific operations, see amd_l3_disable_index() for an example. IOW, I ended up committing this: It looks fine to me except one unwanted/incorrect line in the commit log as mentioned below. I gave it a spin on my i7 box and it works. Thanks for the fix up. --- From: Sudeep Holla Date: Wed, 11 Mar 2015 11:54:29 +0100 Subject: [PATCH] x86/cacheinfo: Fix cache_get_priv_group() for Intel processors The private pointer provided by the cacheinfo code is used to implement the AMD L3 cache-specific attributes using a pointer to the northbridge descriptor. It is needed for performing L3-specific operations and for that we need a couple of PCI devices and other service information, all contained in the northbridge descriptor. However, it's populated even on Intel processors for an L3 cache. After testing this patch, I think I had misunderstood before and it's not populated on Intel processors, so you can drop the line above. Regards, Sudeep -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
On Tue, Mar 10, 2015 at 02:35:12PM +, Sudeep Holla wrote:
> My initial assumption was that it will be NULL for Intel processors
> and hence I assigned cacheinfo->priv to nb pointer unconditionally. So
> I don't have any strong opinion here.
Right, we need the NB descriptor on AMD to do L3-specific operations,
see amd_l3_disable_index() for an example.
IOW, I ended up committing this:
---
From: Sudeep Holla
Date: Wed, 11 Mar 2015 11:54:29 +0100
Subject: [PATCH] x86/cacheinfo: Fix cache_get_priv_group() for Intel
processors
The private pointer provided by the cacheinfo code is used to implement
the AMD L3 cache-specific attributes using a pointer to the northbridge
descriptor. It is needed for performing L3-specific operations and for
that we need a couple of PCI devices and other service information, all
contained in the northbridge descriptor.
However, it's populated even on Intel processors for an L3 cache.
This results in failure of cacheinfo setup as shown below as
cache_get_priv_group() returns the unintialised private attributes which
are not valid for Intel processors.
[ cut here ]
WARNING: CPU: 3 PID: 1 at fs/sysfs/group.c:102
internal_create_group+0x151/0x280()
sysfs: (bin_)attrs not set by subsystem for group: index3/
Modules linked in:
CPU: 3 PID: 1 Comm: swapper/0 Not tainted 4.0.0-rc3+ #1
Hardware name: Dell Inc. Precision T3600/0PTTT9, BIOS A13 05/11/2014
...
Call Trace:
dump_stack
warn_slowpath_common
warn_slowpath_fmt
internal_create_group
sysfs_create_groups
device_add
cpu_device_create
? __kmalloc
cache_add_dev
cacheinfo_sysfs_init
? container_dev_init
do_one_initcall
kernel_init_freeable
? rest_init
kernel_init
ret_from_fork
? rest_init
This patch fixes the issue by checking if the l3 cache indices are
populated correctly (AMD-specific) before initializing the private
attributes.
Reported-by: Borislav Petkov
Signed-off-by: Sudeep Holla
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: "H. Peter Anvin"
Cc: x...@kernel.org
Signed-off-by:
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c
b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 8008bc2dd2d0..edcb0e28c336 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -556,7 +556,7 @@ cache_get_priv_group(struct cacheinfo *this_leaf)
{
struct amd_northbridge *nb = this_leaf->priv;
- if (this_leaf->level < 3)
+ if (this_leaf->level < 3 || !nb)
return NULL;
if (nb && nb->l3_cache.indices)
--
2.2.0.33.gc18b867
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
--
--
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
Hi Boris, On 11/03/15 13:36, Borislav Petkov wrote: On Tue, Mar 10, 2015 at 02:35:12PM +, Sudeep Holla wrote: My initial assumption was that it will be NULL for Intel processors and hence I assigned cacheinfo-priv to nb pointer unconditionally. So I don't have any strong opinion here. Right, we need the NB descriptor on AMD to do L3-specific operations, see amd_l3_disable_index() for an example. IOW, I ended up committing this: It looks fine to me except one unwanted/incorrect line in the commit log as mentioned below. I gave it a spin on my i7 box and it works. Thanks for the fix up. --- From: Sudeep Holla sudeep.ho...@arm.com Date: Wed, 11 Mar 2015 11:54:29 +0100 Subject: [PATCH] x86/cacheinfo: Fix cache_get_priv_group() for Intel processors The private pointer provided by the cacheinfo code is used to implement the AMD L3 cache-specific attributes using a pointer to the northbridge descriptor. It is needed for performing L3-specific operations and for that we need a couple of PCI devices and other service information, all contained in the northbridge descriptor. However, it's populated even on Intel processors for an L3 cache. After testing this patch, I think I had misunderstood before and it's not populated on Intel processors, so you can drop the line above. Regards, Sudeep -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
On Wed, Mar 11, 2015 at 03:44:39PM +, Sudeep Holla wrote: It looks fine to me except one unwanted/incorrect line in the commit log as mentioned below. I gave it a spin on my i7 box and it works. Thanks for the fix up. Thanks for testing. After testing this patch, I think I had misunderstood before and it's not populated on Intel processors, so you can drop the line above. Done. :) -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. -- -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
On Tue, Mar 10, 2015 at 02:35:12PM +, Sudeep Holla wrote:
My initial assumption was that it will be NULL for Intel processors
and hence I assigned cacheinfo-priv to nb pointer unconditionally. So
I don't have any strong opinion here.
Right, we need the NB descriptor on AMD to do L3-specific operations,
see amd_l3_disable_index() for an example.
IOW, I ended up committing this:
---
From: Sudeep Holla sudeep.ho...@arm.com
Date: Wed, 11 Mar 2015 11:54:29 +0100
Subject: [PATCH] x86/cacheinfo: Fix cache_get_priv_group() for Intel
processors
The private pointer provided by the cacheinfo code is used to implement
the AMD L3 cache-specific attributes using a pointer to the northbridge
descriptor. It is needed for performing L3-specific operations and for
that we need a couple of PCI devices and other service information, all
contained in the northbridge descriptor.
However, it's populated even on Intel processors for an L3 cache.
This results in failure of cacheinfo setup as shown below as
cache_get_priv_group() returns the unintialised private attributes which
are not valid for Intel processors.
[ cut here ]
WARNING: CPU: 3 PID: 1 at fs/sysfs/group.c:102
internal_create_group+0x151/0x280()
sysfs: (bin_)attrs not set by subsystem for group: index3/
Modules linked in:
CPU: 3 PID: 1 Comm: swapper/0 Not tainted 4.0.0-rc3+ #1
Hardware name: Dell Inc. Precision T3600/0PTTT9, BIOS A13 05/11/2014
...
Call Trace:
dump_stack
warn_slowpath_common
warn_slowpath_fmt
internal_create_group
sysfs_create_groups
device_add
cpu_device_create
? __kmalloc
cache_add_dev
cacheinfo_sysfs_init
? container_dev_init
do_one_initcall
kernel_init_freeable
? rest_init
kernel_init
ret_from_fork
? rest_init
This patch fixes the issue by checking if the l3 cache indices are
populated correctly (AMD-specific) before initializing the private
attributes.
Reported-by: Borislav Petkov b...@suse.de
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Thomas Gleixner t...@linutronix.de
Cc: Ingo Molnar mi...@redhat.com
Cc: H. Peter Anvin h...@zytor.com
Cc: x...@kernel.org
Signed-off-by:
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c
b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 8008bc2dd2d0..edcb0e28c336 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -556,7 +556,7 @@ cache_get_priv_group(struct cacheinfo *this_leaf)
{
struct amd_northbridge *nb = this_leaf-priv;
- if (this_leaf-level 3)
+ if (this_leaf-level 3 || !nb)
return NULL;
if (nb nb-l3_cache.indices)
--
2.2.0.33.gc18b867
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
--
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
On 10/03/15 14:26, Borislav Petkov wrote: On Tue, Mar 10, 2015 at 02:22:22PM +, Sudeep Holla wrote: I was able to reproduce this and now I realise I had CONFIG_AMD_NB disabled in my config earlier which hid this issue previously, sorry for that. The below patch fixed the issue on my Intel i7 box. I can post this separately if required. Regards, Sudeep From b081cbf26071f4c8ce51f270931387415ab1a06c Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Tue, 10 Mar 2015 13:49:58 + Subject: [PATCH] x86: cacheinfo: fix cache_get_priv_group for Intel processors The private pointer provided by the cacheinfo is used to implement the AMD L3 cache specific attributes using the northbridge pointer obtained through cpuid4 registers. However, it's populated even on Intel processors for Level 3 cache. This results in failure of Do we need it populated on Intel? Because if not, we can leave it NULL there and do only if (this_leaf->level < 3 || !nb) return NULL; Yes we can do that. I leave that too you guys. I don't know the exact reason why cpuid4_cache_lookup_regs is populating struct amd_northbridge *nb in struct _cpuid4_info_reg My initial assumption was that it will be NULL for Intel processors and hence I assigned cacheinfo->priv to nb pointer unconditionally. So I don't have any strong opinion here. Regards, Sudeep -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
On Tue, Mar 10, 2015 at 02:22:22PM +, Sudeep Holla wrote: > I was able to reproduce this and now I realise I had CONFIG_AMD_NB > disabled in my config earlier which hid this issue previously, sorry > for that. > > The below patch fixed the issue on my Intel i7 box. I can post this > separately if required. > > Regards, > Sudeep > > From b081cbf26071f4c8ce51f270931387415ab1a06c Mon Sep 17 00:00:00 2001 > From: Sudeep Holla > Date: Tue, 10 Mar 2015 13:49:58 + > Subject: [PATCH] x86: cacheinfo: fix cache_get_priv_group for Intel > processors > > The private pointer provided by the cacheinfo is used to implement > the AMD L3 cache specific attributes using the northbridge pointer > obtained through cpuid4 registers. However, it's populated even on > Intel processors for Level 3 cache. This results in failure of Do we need it populated on Intel? Because if not, we can leave it NULL there and do only if (this_leaf->level < 3 || !nb) return NULL; No? Thanks. -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. -- -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
On Tue, Mar 10, 2015 at 11:53:35AM +, Sudeep Holla wrote:
Hi Boris,
On 10/03/15 11:37, Borislav Petkov wrote:
> Hi,
>
> I just triggered this is on rc3 + tip/master which has your patch. This
> is an Intel SNB. Ideas, already fixed?
>
No, not seen this before. I will test tip/master on my Intel i7 box
again and get back to you.
I was able to reproduce this and now I realise I had CONFIG_AMD_NB
disabled in my config earlier which hid this issue previously, sorry
for that.
The below patch fixed the issue on my Intel i7 box. I can post this
separately if required.
Regards,
Sudeep
From b081cbf26071f4c8ce51f270931387415ab1a06c Mon Sep 17 00:00:00 2001
From: Sudeep Holla
Date: Tue, 10 Mar 2015 13:49:58 +
Subject: [PATCH] x86: cacheinfo: fix cache_get_priv_group for Intel
processors
The private pointer provided by the cacheinfo is used to implement
the AMD L3 cache specific attributes using the northbridge pointer
obtained through cpuid4 registers. However, it's populated even on
Intel processors for Level 3 cache. This results in failure of
cacheinfo setup as shown below as cache_get_priv_group returns the
unintialised private attributes which are not valid for Intel
processors.
[ cut here ]
WARNING: CPU: 3 PID: 1 at fs/sysfs/group.c:102
internal_create_group+0x151/0x280()
sysfs: (bin_)attrs not set by subsystem for group: index3/
Modules linked in:
CPU: 3 PID: 1 Comm: swapper/0 Not tainted 4.0.0-rc3+ #1
Hardware name: Dell Inc. Precision T3600/0PTTT9, BIOS A13 05/11/2014
81cc6539 88043be73bd8 8184065b
88043be73c28 88043be73c18 8107301a 81eff038
0001 81efef60 81e1c080
Call Trace:
[] dump_stack+0x4f/0x7b
[] warn_slowpath_common+0x8a/0xc0
[] warn_slowpath_fmt+0x46/0x50
[] internal_create_group+0x151/0x280
[] sysfs_create_groups+0x49/0xa0
[] device_add+0x3e3/0x680
[] cpu_device_create+0xc0/0xe0
[] ? __kmalloc+0x20a/0x220
[] cache_add_dev+0x176/0x220
[] cacheinfo_sysfs_init+0x51/0x93
[] ? container_dev_init+0x2f/0x2f
[] do_one_initcall+0xa0/0x200
[] kernel_init_freeable+0x1f5/0x27d
[] ? rest_init+0xd0/0xd0
[] kernel_init+0xe/0xf0
[] ret_from_fork+0x53/0x80
[] ? rest_init+0xd0/0xd0
---[ end trace 5505c77da0d6932a ]---
This patch fixes the issue by checking if the l3 cache indicies are
populated correctly(happens only on AMD processors) before initializing
the private attributes.
Signed-off-by: Sudeep Holla
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: "H. Peter Anvin"
Cc: Borislav Petkov
Cc: x...@kernel.org
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c
b/arch/x86/kernel/cpu/intel_cacheinfo.c
index f98bdebcf047..63b7bb6e8492 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -556,11 +556,10 @@ cache_get_priv_group(struct cacheinfo *this_leaf)
{
struct amd_northbridge *nb = this_leaf->priv;
- if (this_leaf->level < 3)
+ if (this_leaf->level < 3 || !(nb && nb->l3_cache.indices))
return NULL;
- if (nb && nb->l3_cache.indices)
- init_amd_l3_attrs();
+ init_amd_l3_attrs();
return _private_group;
}
--
1.9.1
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
Hi Boris, On 10/03/15 11:37, Borislav Petkov wrote: Hi, I just triggered this is on rc3 + tip/master which has your patch. This is an Intel SNB. Ideas, already fixed? No, not seen this before. I will test tip/master on my Intel i7 box again and get back to you. Regards, Sudeep -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
Hi, I just triggered this is on rc3 + tip/master which has your patch. This is an Intel SNB. Ideas, already fixed? Thanks. [ cut here ] WARNING: CPU: 3 PID: 1 at fs/sysfs/group.c:102 internal_create_group+0x151/0x280() sysfs: (bin_)attrs not set by subsystem for group: index3/ Modules linked in: CPU: 3 PID: 1 Comm: swapper/0 Not tainted 4.0.0-rc3+ #1 Hardware name: Dell Inc. Precision T3600/0PTTT9, BIOS A13 05/11/2014 81cc6539 88043be73bd8 8184065b 88043be73c28 88043be73c18 8107301a 81eff038 0001 81efef60 81e1c080 Call Trace: [] dump_stack+0x4f/0x7b [] warn_slowpath_common+0x8a/0xc0 [] warn_slowpath_fmt+0x46/0x50 [] internal_create_group+0x151/0x280 [] sysfs_create_groups+0x49/0xa0 [] device_add+0x3e3/0x680 [] cpu_device_create+0xc0/0xe0 [] ? __kmalloc+0x20a/0x220 [] cache_add_dev+0x176/0x220 [] cacheinfo_sysfs_init+0x51/0x93 [] ? container_dev_init+0x2f/0x2f [] do_one_initcall+0xa0/0x200 [] kernel_init_freeable+0x1f5/0x27d [] ? rest_init+0xd0/0xd0 [] kernel_init+0xe/0xf0 [] ret_from_fork+0x53/0x80 [] ? rest_init+0xd0/0xd0 ---[ end trace 5505c77da0d6932a ]--- error populating cacheinfo..cpu0 -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. -- -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
Hi Boris, On 10/03/15 11:37, Borislav Petkov wrote: Hi, I just triggered this is on rc3 + tip/master which has your patch. This is an Intel SNB. Ideas, already fixed? No, not seen this before. I will test tip/master on my Intel i7 box again and get back to you. Regards, Sudeep -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
Hi, I just triggered this is on rc3 + tip/master which has your patch. This is an Intel SNB. Ideas, already fixed? Thanks. [ cut here ] WARNING: CPU: 3 PID: 1 at fs/sysfs/group.c:102 internal_create_group+0x151/0x280() sysfs: (bin_)attrs not set by subsystem for group: index3/ Modules linked in: CPU: 3 PID: 1 Comm: swapper/0 Not tainted 4.0.0-rc3+ #1 Hardware name: Dell Inc. Precision T3600/0PTTT9, BIOS A13 05/11/2014 81cc6539 88043be73bd8 8184065b 88043be73c28 88043be73c18 8107301a 81eff038 0001 81efef60 81e1c080 Call Trace: [8184065b] dump_stack+0x4f/0x7b [8107301a] warn_slowpath_common+0x8a/0xc0 [81073096] warn_slowpath_fmt+0x46/0x50 [81277531] internal_create_group+0x151/0x280 [81277799] sysfs_create_groups+0x49/0xa0 [815d8823] device_add+0x3e3/0x680 [815de3d0] cpu_device_create+0xc0/0xe0 [811da78a] ? __kmalloc+0x20a/0x220 [815e15d6] cache_add_dev+0x176/0x220 [81fc3528] cacheinfo_sysfs_init+0x51/0x93 [81fc34d7] ? container_dev_init+0x2f/0x2f [81002110] do_one_initcall+0xa0/0x200 [81f771e5] kernel_init_freeable+0x1f5/0x27d [818345b0] ? rest_init+0xd0/0xd0 [818345be] kernel_init+0xe/0xf0 [8184ad93] ret_from_fork+0x53/0x80 [818345b0] ? rest_init+0xd0/0xd0 ---[ end trace 5505c77da0d6932a ]--- error populating cacheinfo..cpu0 -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. -- -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
On Tue, Mar 10, 2015 at 11:53:35AM +, Sudeep Holla wrote:
Hi Boris,
On 10/03/15 11:37, Borislav Petkov wrote:
Hi,
I just triggered this is on rc3 + tip/master which has your patch. This
is an Intel SNB. Ideas, already fixed?
No, not seen this before. I will test tip/master on my Intel i7 box
again and get back to you.
I was able to reproduce this and now I realise I had CONFIG_AMD_NB
disabled in my config earlier which hid this issue previously, sorry
for that.
The below patch fixed the issue on my Intel i7 box. I can post this
separately if required.
Regards,
Sudeep
From b081cbf26071f4c8ce51f270931387415ab1a06c Mon Sep 17 00:00:00 2001
From: Sudeep Holla sudeep.ho...@arm.com
Date: Tue, 10 Mar 2015 13:49:58 +
Subject: [PATCH] x86: cacheinfo: fix cache_get_priv_group for Intel
processors
The private pointer provided by the cacheinfo is used to implement
the AMD L3 cache specific attributes using the northbridge pointer
obtained through cpuid4 registers. However, it's populated even on
Intel processors for Level 3 cache. This results in failure of
cacheinfo setup as shown below as cache_get_priv_group returns the
unintialised private attributes which are not valid for Intel
processors.
[ cut here ]
WARNING: CPU: 3 PID: 1 at fs/sysfs/group.c:102
internal_create_group+0x151/0x280()
sysfs: (bin_)attrs not set by subsystem for group: index3/
Modules linked in:
CPU: 3 PID: 1 Comm: swapper/0 Not tainted 4.0.0-rc3+ #1
Hardware name: Dell Inc. Precision T3600/0PTTT9, BIOS A13 05/11/2014
81cc6539 88043be73bd8 8184065b
88043be73c28 88043be73c18 8107301a 81eff038
0001 81efef60 81e1c080
Call Trace:
[8184065b] dump_stack+0x4f/0x7b
[8107301a] warn_slowpath_common+0x8a/0xc0
[81073096] warn_slowpath_fmt+0x46/0x50
[81277531] internal_create_group+0x151/0x280
[81277799] sysfs_create_groups+0x49/0xa0
[815d8823] device_add+0x3e3/0x680
[815de3d0] cpu_device_create+0xc0/0xe0
[811da78a] ? __kmalloc+0x20a/0x220
[815e15d6] cache_add_dev+0x176/0x220
[81fc3528] cacheinfo_sysfs_init+0x51/0x93
[81fc34d7] ? container_dev_init+0x2f/0x2f
[81002110] do_one_initcall+0xa0/0x200
[81f771e5] kernel_init_freeable+0x1f5/0x27d
[818345b0] ? rest_init+0xd0/0xd0
[818345be] kernel_init+0xe/0xf0
[8184ad93] ret_from_fork+0x53/0x80
[818345b0] ? rest_init+0xd0/0xd0
---[ end trace 5505c77da0d6932a ]---
This patch fixes the issue by checking if the l3 cache indicies are
populated correctly(happens only on AMD processors) before initializing
the private attributes.
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Thomas Gleixner t...@linutronix.de
Cc: Ingo Molnar mi...@redhat.com
Cc: H. Peter Anvin h...@zytor.com
Cc: Borislav Petkov b...@suse.de
Cc: x...@kernel.org
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c
b/arch/x86/kernel/cpu/intel_cacheinfo.c
index f98bdebcf047..63b7bb6e8492 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -556,11 +556,10 @@ cache_get_priv_group(struct cacheinfo *this_leaf)
{
struct amd_northbridge *nb = this_leaf-priv;
- if (this_leaf-level 3)
+ if (this_leaf-level 3 || !(nb nb-l3_cache.indices))
return NULL;
- if (nb nb-l3_cache.indices)
- init_amd_l3_attrs();
+ init_amd_l3_attrs();
return cache_private_group;
}
--
1.9.1
--
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Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
On Tue, Mar 10, 2015 at 02:22:22PM +, Sudeep Holla wrote: I was able to reproduce this and now I realise I had CONFIG_AMD_NB disabled in my config earlier which hid this issue previously, sorry for that. The below patch fixed the issue on my Intel i7 box. I can post this separately if required. Regards, Sudeep From b081cbf26071f4c8ce51f270931387415ab1a06c Mon Sep 17 00:00:00 2001 From: Sudeep Holla sudeep.ho...@arm.com Date: Tue, 10 Mar 2015 13:49:58 + Subject: [PATCH] x86: cacheinfo: fix cache_get_priv_group for Intel processors The private pointer provided by the cacheinfo is used to implement the AMD L3 cache specific attributes using the northbridge pointer obtained through cpuid4 registers. However, it's populated even on Intel processors for Level 3 cache. This results in failure of Do we need it populated on Intel? Because if not, we can leave it NULL there and do only if (this_leaf-level 3 || !nb) return NULL; No? Thanks. -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. -- -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
On 10/03/15 14:26, Borislav Petkov wrote: On Tue, Mar 10, 2015 at 02:22:22PM +, Sudeep Holla wrote: I was able to reproduce this and now I realise I had CONFIG_AMD_NB disabled in my config earlier which hid this issue previously, sorry for that. The below patch fixed the issue on my Intel i7 box. I can post this separately if required. Regards, Sudeep From b081cbf26071f4c8ce51f270931387415ab1a06c Mon Sep 17 00:00:00 2001 From: Sudeep Holla sudeep.ho...@arm.com Date: Tue, 10 Mar 2015 13:49:58 + Subject: [PATCH] x86: cacheinfo: fix cache_get_priv_group for Intel processors The private pointer provided by the cacheinfo is used to implement the AMD L3 cache specific attributes using the northbridge pointer obtained through cpuid4 registers. However, it's populated even on Intel processors for Level 3 cache. This results in failure of Do we need it populated on Intel? Because if not, we can leave it NULL there and do only if (this_leaf-level 3 || !nb) return NULL; Yes we can do that. I leave that too you guys. I don't know the exact reason why cpuid4_cache_lookup_regs is populating struct amd_northbridge *nb in struct _cpuid4_info_reg My initial assumption was that it will be NULL for Intel processors and hence I assigned cacheinfo-priv to nb pointer unconditionally. So I don't have any strong opinion here. Regards, Sudeep -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
Hi Boris,
On 05/03/15 08:16, Borislav Petkov wrote:
On Wed, Mar 04, 2015 at 01:27:20PM +0100, Borislav Petkov wrote:
Applied, thanks guys.
Ok, we forgot to add the same check in the cpu_has_topoext case in
__cache_amd_cpumap_setup() and my F15h exploded this morning:
---
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c
b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 54e43d58e714..8008bc2dd2d0 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -820,9 +820,13 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, int
index,
for_each_online_cpu(i) {
this_cpu_ci = get_cpu_cacheinfo(i);
+ if (!this_cpu_ci->info_list)
+ continue;
+
apicid = cpu_data(i).apicid;
if ((apicid < first) || (apicid > last))
continue;
+
this_leaf = this_cpu_ci->info_list + index;
for_each_online_cpu(sibling) {
---
I've folded the above into your patch.
Thanks a lot.
--
Regards,
Sudeep
--
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Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
On Wed, Mar 04, 2015 at 01:27:20PM +0100, Borislav Petkov wrote:
> Applied, thanks guys.
Ok, we forgot to add the same check in the cpu_has_topoext case in
__cache_amd_cpumap_setup() and my F15h exploded this morning:
---
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c
b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 54e43d58e714..8008bc2dd2d0 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -820,9 +820,13 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, int
index,
for_each_online_cpu(i) {
this_cpu_ci = get_cpu_cacheinfo(i);
+ if (!this_cpu_ci->info_list)
+ continue;
+
apicid = cpu_data(i).apicid;
if ((apicid < first) || (apicid > last))
continue;
+
this_leaf = this_cpu_ci->info_list + index;
for_each_online_cpu(sibling) {
---
I've folded the above into your patch.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
--
--
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
On Wed, Mar 04, 2015 at 01:27:20PM +0100, Borislav Petkov wrote:
Applied, thanks guys.
Ok, we forgot to add the same check in the cpu_has_topoext case in
__cache_amd_cpumap_setup() and my F15h exploded this morning:
---
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c
b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 54e43d58e714..8008bc2dd2d0 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -820,9 +820,13 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, int
index,
for_each_online_cpu(i) {
this_cpu_ci = get_cpu_cacheinfo(i);
+ if (!this_cpu_ci-info_list)
+ continue;
+
apicid = cpu_data(i).apicid;
if ((apicid first) || (apicid last))
continue;
+
this_leaf = this_cpu_ci-info_list + index;
for_each_online_cpu(sibling) {
---
I've folded the above into your patch.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
--
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
Hi Boris,
On 05/03/15 08:16, Borislav Petkov wrote:
On Wed, Mar 04, 2015 at 01:27:20PM +0100, Borislav Petkov wrote:
Applied, thanks guys.
Ok, we forgot to add the same check in the cpu_has_topoext case in
__cache_amd_cpumap_setup() and my F15h exploded this morning:
---
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c
b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 54e43d58e714..8008bc2dd2d0 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -820,9 +820,13 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, int
index,
for_each_online_cpu(i) {
this_cpu_ci = get_cpu_cacheinfo(i);
+ if (!this_cpu_ci-info_list)
+ continue;
+
apicid = cpu_data(i).apicid;
if ((apicid first) || (apicid last))
continue;
+
this_leaf = this_cpu_ci-info_list + index;
for_each_online_cpu(sibling) {
---
I've folded the above into your patch.
Thanks a lot.
--
Regards,
Sudeep
--
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
On Wed, Mar 04, 2015 at 12:00:16PM +, Sudeep Holla wrote:
> This patch removes the redundant sysfs cacheinfo code by reusing
> the newly introduced generic cacheinfo infrastructure through the
> commit 246246cbde5e ("drivers: base: support cpu cache information
> interface to userspace via sysfs")
>
> The private pointer provided by the cacheinfo is used to implement
> the AMD L3 cache specific attributes.
>
> Note that with v4.0-rc1, commit 513e3d2d11c9 ("cpumask: always use
> nr_cpu_ids in formatting and parsing functions") in particular changes
> from long format to shorter one for all cpumasks sysfs entries. As the
> consequence of the same, even the shared_cpu_map in the cacheinfo sysfs
> was also changed.
>
> This patch neither alters any existing sysfs entries nor their formating,
> however since the generic cacheinfo has switched to use the device
> attributes instead of the traditional raw kobjects, a directory named
> "power" along with its standard attributes are added similar to any
> other device.
>
> Signed-off-by: Sudeep Holla
> Cc: Thomas Gleixner
> Cc: Ingo Molnar
> Cc: "H. Peter Anvin"
> Cc: Borislav Petkov
> Cc: Andre Przywara
> Cc: x...@kernel.org
Applied, thanks guys.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
--
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
This patch removes the redundant sysfs cacheinfo code by reusing
the newly introduced generic cacheinfo infrastructure through the
commit 246246cbde5e ("drivers: base: support cpu cache information
interface to userspace via sysfs")
The private pointer provided by the cacheinfo is used to implement
the AMD L3 cache specific attributes.
Note that with v4.0-rc1, commit 513e3d2d11c9 ("cpumask: always use
nr_cpu_ids in formatting and parsing functions") in particular changes
from long format to shorter one for all cpumasks sysfs entries. As the
consequence of the same, even the shared_cpu_map in the cacheinfo sysfs
was also changed.
This patch neither alters any existing sysfs entries nor their formating,
however since the generic cacheinfo has switched to use the device
attributes instead of the traditional raw kobjects, a directory named
"power" along with its standard attributes are added similar to any
other device.
Signed-off-by: Sudeep Holla
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: "H. Peter Anvin"
Cc: Borislav Petkov
Cc: Andre Przywara
Cc: x...@kernel.org
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 711 ++
1 file changed, 194 insertions(+), 517 deletions(-)
v2->v3:
- Fixed the NULL pointer deference that occured as a check was missed
when migrating to generic cacheinfo. Thanks to Andre Przywara for
debugging the same and Borislav Petkov for suggesting the fix.
- Added a note in the commit log regarding the recent change in
cpumask sysfs formating.
v1->v2:
- Rebased on v4.0-rc1
- Fixed lockdep warning reported by Borislav
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c
b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 659643376dbf..54e43d58e714 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -7,16 +7,14 @@
* Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD.
*/
-#include
#include
-#include
-#include
+#include
#include
#include
+#include
#include
#include
-#include
#include
#include
@@ -116,10 +114,10 @@ static const struct _cache_table cache_table[] =
enum _cache_type {
- CACHE_TYPE_NULL = 0,
- CACHE_TYPE_DATA = 1,
- CACHE_TYPE_INST = 2,
- CACHE_TYPE_UNIFIED = 3
+ CTYPE_NULL = 0,
+ CTYPE_DATA = 1,
+ CTYPE_INST = 2,
+ CTYPE_UNIFIED = 3
};
union _cpuid4_leaf_eax {
@@ -159,11 +157,6 @@ struct _cpuid4_info_regs {
struct amd_northbridge *nb;
};
-struct _cpuid4_info {
- struct _cpuid4_info_regs base;
- DECLARE_BITMAP(shared_cpu_map, NR_CPUS);
-};
-
unsigned short num_cache_leaves;
/* AMD doesn't have CPUID4. Emulate it here to report the same
@@ -220,6 +213,13 @@ static const unsigned short assocs[] = {
static const unsigned char levels[] = { 1, 1, 2, 3 };
static const unsigned char types[] = { 1, 2, 3, 3 };
+static const enum cache_type cache_type_map[] = {
+ [CTYPE_NULL] = CACHE_TYPE_NOCACHE,
+ [CTYPE_DATA] = CACHE_TYPE_DATA,
+ [CTYPE_INST] = CACHE_TYPE_INST,
+ [CTYPE_UNIFIED] = CACHE_TYPE_UNIFIED,
+};
+
static void
amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
union _cpuid4_leaf_ebx *ebx,
@@ -291,14 +291,8 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
(ebx->split.ways_of_associativity + 1) - 1;
}
-struct _cache_attr {
- struct attribute attr;
- ssize_t (*show)(struct _cpuid4_info *, char *, unsigned int);
- ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count,
-unsigned int);
-};
-
#if defined(CONFIG_AMD_NB) && defined(CONFIG_SYSFS)
+
/*
* L3 cache descriptors
*/
@@ -325,20 +319,6 @@ static void amd_calc_l3_indices(struct amd_northbridge *nb)
l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1;
}
-static void amd_init_l3_cache(struct _cpuid4_info_regs *this_leaf, int index)
-{
- int node;
-
- /* only for L3, and not in virtualized environments */
- if (index < 3)
- return;
-
- node = amd_get_nb_id(smp_processor_id());
- this_leaf->nb = node_to_amd_nb(node);
- if (this_leaf->nb && !this_leaf->nb->l3_cache.indices)
- amd_calc_l3_indices(this_leaf->nb);
-}
-
/*
* check whether a slot used for disabling an L3 index is occupied.
* @l3: L3 cache descriptor
@@ -359,15 +339,13 @@ int amd_get_l3_disable_slot(struct amd_northbridge *nb,
unsigned slot)
return -1;
}
-static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
+static ssize_t show_cache_disable(struct cacheinfo *this_leaf, char *buf,
unsigned int slot)
{
int index;
+ struct amd_northbridge *nb = this_leaf->priv;
- if (!this_leaf->base.nb || !amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE))
- return -EINVAL;
-
- index = amd_get_l3_disable_slot(this_leaf->base.nb, slot);
+ index =
[PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
This patch removes the redundant sysfs cacheinfo code by reusing
the newly introduced generic cacheinfo infrastructure through the
commit 246246cbde5e (drivers: base: support cpu cache information
interface to userspace via sysfs)
The private pointer provided by the cacheinfo is used to implement
the AMD L3 cache specific attributes.
Note that with v4.0-rc1, commit 513e3d2d11c9 (cpumask: always use
nr_cpu_ids in formatting and parsing functions) in particular changes
from long format to shorter one for all cpumasks sysfs entries. As the
consequence of the same, even the shared_cpu_map in the cacheinfo sysfs
was also changed.
This patch neither alters any existing sysfs entries nor their formating,
however since the generic cacheinfo has switched to use the device
attributes instead of the traditional raw kobjects, a directory named
power along with its standard attributes are added similar to any
other device.
Signed-off-by: Sudeep Holla sudeep.ho...@arm.com
Cc: Thomas Gleixner t...@linutronix.de
Cc: Ingo Molnar mi...@redhat.com
Cc: H. Peter Anvin h...@zytor.com
Cc: Borislav Petkov b...@suse.de
Cc: Andre Przywara andre.przyw...@arm.com
Cc: x...@kernel.org
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 711 ++
1 file changed, 194 insertions(+), 517 deletions(-)
v2-v3:
- Fixed the NULL pointer deference that occured as a check was missed
when migrating to generic cacheinfo. Thanks to Andre Przywara for
debugging the same and Borislav Petkov for suggesting the fix.
- Added a note in the commit log regarding the recent change in
cpumask sysfs formating.
v1-v2:
- Rebased on v4.0-rc1
- Fixed lockdep warning reported by Borislav
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c
b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 659643376dbf..54e43d58e714 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -7,16 +7,14 @@
* Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD.
*/
-#include linux/init.h
#include linux/slab.h
-#include linux/device.h
-#include linux/compiler.h
+#include linux/cacheinfo.h
#include linux/cpu.h
#include linux/sched.h
+#include linux/sysfs.h
#include linux/pci.h
#include asm/processor.h
-#include linux/smp.h
#include asm/amd_nb.h
#include asm/smp.h
@@ -116,10 +114,10 @@ static const struct _cache_table cache_table[] =
enum _cache_type {
- CACHE_TYPE_NULL = 0,
- CACHE_TYPE_DATA = 1,
- CACHE_TYPE_INST = 2,
- CACHE_TYPE_UNIFIED = 3
+ CTYPE_NULL = 0,
+ CTYPE_DATA = 1,
+ CTYPE_INST = 2,
+ CTYPE_UNIFIED = 3
};
union _cpuid4_leaf_eax {
@@ -159,11 +157,6 @@ struct _cpuid4_info_regs {
struct amd_northbridge *nb;
};
-struct _cpuid4_info {
- struct _cpuid4_info_regs base;
- DECLARE_BITMAP(shared_cpu_map, NR_CPUS);
-};
-
unsigned short num_cache_leaves;
/* AMD doesn't have CPUID4. Emulate it here to report the same
@@ -220,6 +213,13 @@ static const unsigned short assocs[] = {
static const unsigned char levels[] = { 1, 1, 2, 3 };
static const unsigned char types[] = { 1, 2, 3, 3 };
+static const enum cache_type cache_type_map[] = {
+ [CTYPE_NULL] = CACHE_TYPE_NOCACHE,
+ [CTYPE_DATA] = CACHE_TYPE_DATA,
+ [CTYPE_INST] = CACHE_TYPE_INST,
+ [CTYPE_UNIFIED] = CACHE_TYPE_UNIFIED,
+};
+
static void
amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
union _cpuid4_leaf_ebx *ebx,
@@ -291,14 +291,8 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
(ebx-split.ways_of_associativity + 1) - 1;
}
-struct _cache_attr {
- struct attribute attr;
- ssize_t (*show)(struct _cpuid4_info *, char *, unsigned int);
- ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count,
-unsigned int);
-};
-
#if defined(CONFIG_AMD_NB) defined(CONFIG_SYSFS)
+
/*
* L3 cache descriptors
*/
@@ -325,20 +319,6 @@ static void amd_calc_l3_indices(struct amd_northbridge *nb)
l3-indices = (max(max3(sc0, sc1, sc2), sc3) 10) - 1;
}
-static void amd_init_l3_cache(struct _cpuid4_info_regs *this_leaf, int index)
-{
- int node;
-
- /* only for L3, and not in virtualized environments */
- if (index 3)
- return;
-
- node = amd_get_nb_id(smp_processor_id());
- this_leaf-nb = node_to_amd_nb(node);
- if (this_leaf-nb !this_leaf-nb-l3_cache.indices)
- amd_calc_l3_indices(this_leaf-nb);
-}
-
/*
* check whether a slot used for disabling an L3 index is occupied.
* @l3: L3 cache descriptor
@@ -359,15 +339,13 @@ int amd_get_l3_disable_slot(struct amd_northbridge *nb,
unsigned slot)
return -1;
}
-static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
+static ssize_t show_cache_disable(struct cacheinfo *this_leaf, char *buf,
unsigned int slot)
{
int index;
+
Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure
On Wed, Mar 04, 2015 at 12:00:16PM +, Sudeep Holla wrote: This patch removes the redundant sysfs cacheinfo code by reusing the newly introduced generic cacheinfo infrastructure through the commit 246246cbde5e (drivers: base: support cpu cache information interface to userspace via sysfs) The private pointer provided by the cacheinfo is used to implement the AMD L3 cache specific attributes. Note that with v4.0-rc1, commit 513e3d2d11c9 (cpumask: always use nr_cpu_ids in formatting and parsing functions) in particular changes from long format to shorter one for all cpumasks sysfs entries. As the consequence of the same, even the shared_cpu_map in the cacheinfo sysfs was also changed. This patch neither alters any existing sysfs entries nor their formating, however since the generic cacheinfo has switched to use the device attributes instead of the traditional raw kobjects, a directory named power along with its standard attributes are added similar to any other device. Signed-off-by: Sudeep Holla sudeep.ho...@arm.com Cc: Thomas Gleixner t...@linutronix.de Cc: Ingo Molnar mi...@redhat.com Cc: H. Peter Anvin h...@zytor.com Cc: Borislav Petkov b...@suse.de Cc: Andre Przywara andre.przyw...@arm.com Cc: x...@kernel.org Applied, thanks guys. -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. -- -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
