Re: [PATCH v3 1/2] pinctrl: qcom: Add sdm660 pinctrl driver
On Wed, Sep 26, 2018 at 6:30 PM Craig wrote: > You seem to have missed the bindings, it might be an idea to drop and reapply > with the new ones I just sent off when they get a review. Nah I just didn't coordinate things. It gets too messy sometimes, I will apply the bindings separately I guess. Yours, Linus Walleij
Re: [PATCH v3 1/2] pinctrl: qcom: Add sdm660 pinctrl driver
On Wed, Sep 26, 2018 at 6:30 PM Craig wrote: > You seem to have missed the bindings, it might be an idea to drop and reapply > with the new ones I just sent off when they get a review. Nah I just didn't coordinate things. It gets too messy sometimes, I will apply the bindings separately I guess. Yours, Linus Walleij
Re: [PATCH v3 1/2] pinctrl: qcom: Add sdm660 pinctrl driver
Hey, You seem to have missed the bindings, it might be an idea to drop and reapply with the new ones I just sent off when they get a review. On 26 September 2018 07:57:41 BST, Linus Walleij wrote: >On Tue, Sep 25, 2018 at 7:38 PM Craig Tatlor >wrote: > >> From: Neeraj Upadhyay >> >> Add initial pinctrl driver to support pin configuration with >> pinctrl framework for sdm660. >> Based off CAF implementation. >> >> Signed-off-by: Neeraj Upadhyay >> Co-Developed-by: Venkatesh Yadav Abbarapu >> Signed-off-by: Venkatesh Yadav Abbarapu >> [craig: minor updates for upstreaming, updated tile handling] >> Signed-off-by: Craig Tatlor > >Co-Developed-by? That was innovative. > >Anyways, since there is also a signoff all is fine. > >Patch applied with Björn's ACK. > >Yours, >Linus Walleij -- Sent from my Android device with K-9 Mail. Please excuse my brevity.
Re: [PATCH v3 1/2] pinctrl: qcom: Add sdm660 pinctrl driver
Hey, You seem to have missed the bindings, it might be an idea to drop and reapply with the new ones I just sent off when they get a review. On 26 September 2018 07:57:41 BST, Linus Walleij wrote: >On Tue, Sep 25, 2018 at 7:38 PM Craig Tatlor >wrote: > >> From: Neeraj Upadhyay >> >> Add initial pinctrl driver to support pin configuration with >> pinctrl framework for sdm660. >> Based off CAF implementation. >> >> Signed-off-by: Neeraj Upadhyay >> Co-Developed-by: Venkatesh Yadav Abbarapu >> Signed-off-by: Venkatesh Yadav Abbarapu >> [craig: minor updates for upstreaming, updated tile handling] >> Signed-off-by: Craig Tatlor > >Co-Developed-by? That was innovative. > >Anyways, since there is also a signoff all is fine. > >Patch applied with Björn's ACK. > >Yours, >Linus Walleij -- Sent from my Android device with K-9 Mail. Please excuse my brevity.
Re: [PATCH v3 1/2] pinctrl: qcom: Add sdm660 pinctrl driver
On Tue, Sep 25, 2018 at 7:38 PM Craig Tatlor wrote: > From: Neeraj Upadhyay > > Add initial pinctrl driver to support pin configuration with > pinctrl framework for sdm660. > Based off CAF implementation. > > Signed-off-by: Neeraj Upadhyay > Co-Developed-by: Venkatesh Yadav Abbarapu > Signed-off-by: Venkatesh Yadav Abbarapu > [craig: minor updates for upstreaming, updated tile handling] > Signed-off-by: Craig Tatlor Co-Developed-by? That was innovative. Anyways, since there is also a signoff all is fine. Patch applied with Björn's ACK. Yours, Linus Walleij
Re: [PATCH v3 1/2] pinctrl: qcom: Add sdm660 pinctrl driver
On Tue, Sep 25, 2018 at 7:38 PM Craig Tatlor wrote: > From: Neeraj Upadhyay > > Add initial pinctrl driver to support pin configuration with > pinctrl framework for sdm660. > Based off CAF implementation. > > Signed-off-by: Neeraj Upadhyay > Co-Developed-by: Venkatesh Yadav Abbarapu > Signed-off-by: Venkatesh Yadav Abbarapu > [craig: minor updates for upstreaming, updated tile handling] > Signed-off-by: Craig Tatlor Co-Developed-by? That was innovative. Anyways, since there is also a signoff all is fine. Patch applied with Björn's ACK. Yours, Linus Walleij
Re: [PATCH v3 1/2] pinctrl: qcom: Add sdm660 pinctrl driver
On Tue 25 Sep 10:37 PDT 2018, Craig Tatlor wrote:
> From: Neeraj Upadhyay
>
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for sdm660.
> Based off CAF implementation.
>
> Signed-off-by: Neeraj Upadhyay
> Co-Developed-by: Venkatesh Yadav Abbarapu
> Signed-off-by: Venkatesh Yadav Abbarapu
> [craig: minor updates for upstreaming, updated tile handling]
> Signed-off-by: Craig Tatlor
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
> drivers/pinctrl/qcom/Kconfig |9 +
> drivers/pinctrl/qcom/Makefile |1 +
> drivers/pinctrl/qcom/pinctrl-sdm660.c | 1455 +
> 3 files changed, 1465 insertions(+)
> create mode 100644 drivers/pinctrl/qcom/pinctrl-sdm660.c
>
> Changes from V2:
> Sort everything
> Use tiles
> Add sdm630 compatible
>
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index c17bfe3a93ea..836e9f3eae4c 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -155,6 +155,15 @@ config PINCTRL_QCOM_SSBI_PMIC
> which are using SSBI for communication with SoC. Example PMIC's
> devices are pm8058 and pm8921.
>
> +config PINCTRL_SDM660
> + tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
> + depends on GPIOLIB && OF
> + select PINCTRL_MSM
> + help
> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> + Qualcomm Technologies Inc TLMM block found on the Qualcomm
> + Technologies Inc SDM660 platform.
> +
> config PINCTRL_SDM845
> tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
> depends on GPIOLIB && OF
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index 98b18b8cd2cc..344b4c6a6c6e 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -20,4 +20,5 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
> obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
> obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
> obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
> +obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
> obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660.c
> b/drivers/pinctrl/qcom/pinctrl-sdm660.c
> new file mode 100644
> index ..6838b38555a1
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c
> @@ -0,0 +1,1455 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2018, Craig Tatlor.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#include "pinctrl-msm.h"
> +
> +static const char * const sdm660_tiles[] = {
> + "north",
> + "center",
> + "south"
> +};
> +
> +enum {
> + NORTH,
> + CENTER,
> + SOUTH
> +};
> +
> +#define REG_SIZE 0x1000
> +
> +#define FUNCTION(fname) \
> + [msm_mux_##fname] = { \
> + .name = #fname, \
> + .groups = fname##_groups, \
> + .ngroups = ARRAY_SIZE(fname##_groups), \
> + }
> +
> +
> +#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
> + { \
> + .name = "gpio" #id, \
> + .pins = gpio##id##_pins,\
> + .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
> + .funcs = (int[]){ \
> + msm_mux_gpio, /* gpio mode */ \
> + msm_mux_##f1, \
> + msm_mux_##f2, \
> + msm_mux_##f3, \
> + msm_mux_##f4, \
> + msm_mux_##f5, \
> + msm_mux_##f6, \
> + msm_mux_##f7, \
> + msm_mux_##f8, \
> + msm_mux_##f9\
> + }, \
> + .nfuncs = 10, \
> + .ctl_reg = base + REG_SIZE * id,\
> + .io_reg = base + 0x4 + REG_SIZE * id, \
> + .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
> + .intr_status_reg = base + 0xc + REG_SIZE * id, \
> + .intr_target_reg = base + 0x8 + REG_SIZE * id, \
> + .mux_bit = 2, \
> + .pull_bit = 0, \
> + .drv_bit = 6, \
> + .oe_bit = 9,\
> + .in_bit = 0,\
> + .out_bit = 1,
Re: [PATCH v3 1/2] pinctrl: qcom: Add sdm660 pinctrl driver
On Tue 25 Sep 10:37 PDT 2018, Craig Tatlor wrote:
> From: Neeraj Upadhyay
>
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for sdm660.
> Based off CAF implementation.
>
> Signed-off-by: Neeraj Upadhyay
> Co-Developed-by: Venkatesh Yadav Abbarapu
> Signed-off-by: Venkatesh Yadav Abbarapu
> [craig: minor updates for upstreaming, updated tile handling]
> Signed-off-by: Craig Tatlor
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
> drivers/pinctrl/qcom/Kconfig |9 +
> drivers/pinctrl/qcom/Makefile |1 +
> drivers/pinctrl/qcom/pinctrl-sdm660.c | 1455 +
> 3 files changed, 1465 insertions(+)
> create mode 100644 drivers/pinctrl/qcom/pinctrl-sdm660.c
>
> Changes from V2:
> Sort everything
> Use tiles
> Add sdm630 compatible
>
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index c17bfe3a93ea..836e9f3eae4c 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -155,6 +155,15 @@ config PINCTRL_QCOM_SSBI_PMIC
> which are using SSBI for communication with SoC. Example PMIC's
> devices are pm8058 and pm8921.
>
> +config PINCTRL_SDM660
> + tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
> + depends on GPIOLIB && OF
> + select PINCTRL_MSM
> + help
> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> + Qualcomm Technologies Inc TLMM block found on the Qualcomm
> + Technologies Inc SDM660 platform.
> +
> config PINCTRL_SDM845
> tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
> depends on GPIOLIB && OF
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index 98b18b8cd2cc..344b4c6a6c6e 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -20,4 +20,5 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
> obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
> obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
> obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
> +obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
> obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660.c
> b/drivers/pinctrl/qcom/pinctrl-sdm660.c
> new file mode 100644
> index ..6838b38555a1
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c
> @@ -0,0 +1,1455 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2018, Craig Tatlor.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#include "pinctrl-msm.h"
> +
> +static const char * const sdm660_tiles[] = {
> + "north",
> + "center",
> + "south"
> +};
> +
> +enum {
> + NORTH,
> + CENTER,
> + SOUTH
> +};
> +
> +#define REG_SIZE 0x1000
> +
> +#define FUNCTION(fname) \
> + [msm_mux_##fname] = { \
> + .name = #fname, \
> + .groups = fname##_groups, \
> + .ngroups = ARRAY_SIZE(fname##_groups), \
> + }
> +
> +
> +#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
> + { \
> + .name = "gpio" #id, \
> + .pins = gpio##id##_pins,\
> + .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
> + .funcs = (int[]){ \
> + msm_mux_gpio, /* gpio mode */ \
> + msm_mux_##f1, \
> + msm_mux_##f2, \
> + msm_mux_##f3, \
> + msm_mux_##f4, \
> + msm_mux_##f5, \
> + msm_mux_##f6, \
> + msm_mux_##f7, \
> + msm_mux_##f8, \
> + msm_mux_##f9\
> + }, \
> + .nfuncs = 10, \
> + .ctl_reg = base + REG_SIZE * id,\
> + .io_reg = base + 0x4 + REG_SIZE * id, \
> + .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
> + .intr_status_reg = base + 0xc + REG_SIZE * id, \
> + .intr_target_reg = base + 0x8 + REG_SIZE * id, \
> + .mux_bit = 2, \
> + .pull_bit = 0, \
> + .drv_bit = 6, \
> + .oe_bit = 9,\
> + .in_bit = 0,\
> + .out_bit = 1,
[PATCH v3 1/2] pinctrl: qcom: Add sdm660 pinctrl driver
From: Neeraj Upadhyay
Add initial pinctrl driver to support pin configuration with
pinctrl framework for sdm660.
Based off CAF implementation.
Signed-off-by: Neeraj Upadhyay
Co-Developed-by: Venkatesh Yadav Abbarapu
Signed-off-by: Venkatesh Yadav Abbarapu
[craig: minor updates for upstreaming, updated tile handling]
Signed-off-by: Craig Tatlor
---
drivers/pinctrl/qcom/Kconfig |9 +
drivers/pinctrl/qcom/Makefile |1 +
drivers/pinctrl/qcom/pinctrl-sdm660.c | 1455 +
3 files changed, 1465 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-sdm660.c
Changes from V2:
Sort everything
Use tiles
Add sdm630 compatible
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index c17bfe3a93ea..836e9f3eae4c 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -155,6 +155,15 @@ config PINCTRL_QCOM_SSBI_PMIC
which are using SSBI for communication with SoC. Example PMIC's
devices are pm8058 and pm8921.
+config PINCTRL_SDM660
+ tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc SDM660 platform.
+
config PINCTRL_SDM845
tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
depends on GPIOLIB && OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 98b18b8cd2cc..344b4c6a6c6e 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -20,4 +20,5 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
+obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660.c
b/drivers/pinctrl/qcom/pinctrl-sdm660.c
new file mode 100644
index ..6838b38555a1
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c
@@ -0,0 +1,1455 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, Craig Tatlor.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "pinctrl-msm.h"
+
+static const char * const sdm660_tiles[] = {
+ "north",
+ "center",
+ "south"
+};
+
+enum {
+ NORTH,
+ CENTER,
+ SOUTH
+};
+
+#define REG_SIZE 0x1000
+
+#define FUNCTION(fname)\
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+
+#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins,\
+ .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9\
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = base + REG_SIZE * id,\
+ .io_reg = base + 0x4 + REG_SIZE * id, \
+ .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
+ .intr_status_reg = base + 0xc + REG_SIZE * id, \
+ .intr_target_reg = base + 0x8 + REG_SIZE * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9,\
+ .in_bit = 0,\
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+
[PATCH v3 1/2] pinctrl: qcom: Add sdm660 pinctrl driver
From: Neeraj Upadhyay
Add initial pinctrl driver to support pin configuration with
pinctrl framework for sdm660.
Based off CAF implementation.
Signed-off-by: Neeraj Upadhyay
Co-Developed-by: Venkatesh Yadav Abbarapu
Signed-off-by: Venkatesh Yadav Abbarapu
[craig: minor updates for upstreaming, updated tile handling]
Signed-off-by: Craig Tatlor
---
drivers/pinctrl/qcom/Kconfig |9 +
drivers/pinctrl/qcom/Makefile |1 +
drivers/pinctrl/qcom/pinctrl-sdm660.c | 1455 +
3 files changed, 1465 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-sdm660.c
Changes from V2:
Sort everything
Use tiles
Add sdm630 compatible
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index c17bfe3a93ea..836e9f3eae4c 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -155,6 +155,15 @@ config PINCTRL_QCOM_SSBI_PMIC
which are using SSBI for communication with SoC. Example PMIC's
devices are pm8058 and pm8921.
+config PINCTRL_SDM660
+ tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc SDM660 platform.
+
config PINCTRL_SDM845
tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
depends on GPIOLIB && OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 98b18b8cd2cc..344b4c6a6c6e 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -20,4 +20,5 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
+obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660.c
b/drivers/pinctrl/qcom/pinctrl-sdm660.c
new file mode 100644
index ..6838b38555a1
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c
@@ -0,0 +1,1455 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, Craig Tatlor.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "pinctrl-msm.h"
+
+static const char * const sdm660_tiles[] = {
+ "north",
+ "center",
+ "south"
+};
+
+enum {
+ NORTH,
+ CENTER,
+ SOUTH
+};
+
+#define REG_SIZE 0x1000
+
+#define FUNCTION(fname)\
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+
+#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins,\
+ .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9\
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = base + REG_SIZE * id,\
+ .io_reg = base + 0x4 + REG_SIZE * id, \
+ .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
+ .intr_status_reg = base + 0xc + REG_SIZE * id, \
+ .intr_target_reg = base + 0x8 + REG_SIZE * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9,\
+ .in_bit = 0,\
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+
