RE: [PATCH v3 2/2] spi: add SPI controller driver for UniPhier SoC
Hi Andy,
Thank you for your check.
> From: Andy Shevchenko [mailto:andy.shevche...@gmail.com]
> Sent: Wednesday, August 1, 2018 7:21 PM
> To: Hayashibara, Keiji/林原 啓二
> Subject: Re: [PATCH v3 2/2] spi: add SPI controller driver for UniPhier SoC
>
> On Wed, Aug 1, 2018 at 10:29 AM, Keiji Hayashibara
> wrote:
> > Add SPI controller driver implemented in Socionext UniPhier SoCs.
> >
> > UniPhier SoCs have two types SPI controllers; SCSSI supports a single
> > channel, and MCSSI supports multiple channels.
> > This driver supports SCSSI only.
> >
> > This controller has 32bit TX/RX FIFO with depth of eight entry, and
> > supports the SPI master mode only.
> >
> > This commit is implemented in PIO transfer mode, not DMA transfer.
> >
>
> One comment below, otherwise FWIW,
> Reviewed-by: Andy Shevchenko
>
>
> > Signed-off-by: Kunihiko Hayashi
> > Signed-off-by: Keiji Hayashibara
> > ---
> > drivers/spi/Kconfig| 13 ++
> > drivers/spi/Makefile | 1 +
> > drivers/spi/spi-uniphier.c | 525
> > +
> > 3 files changed, 539 insertions(+)
> > create mode 100644 drivers/spi/spi-uniphier.c
> >
> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index
> > ad5d68e..671d078 100644
> > --- a/drivers/spi/Kconfig
> > +++ b/drivers/spi/Kconfig
> > @@ -688,6 +688,19 @@ config SPI_TXX9
> > help
> > SPI driver for Toshiba TXx9 MIPS SoCs
> >
> > +config SPI_UNIPHIER
> > + tristate "Socionext UniPhier SPI Controller"
> > + depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
> > + help
> > + This enables a driver for the Socionext UniPhier SoC SCSSI SPI
> > controller.
> > +
> > + UniPhier SoCs have SCSSI and MCSSI SPI controllers.
> > + Every UniPhier SoC has SCSSI which supports single channel.
> > + Older UniPhier Pro4/Pro5 also has MCSSI which support multiple
> > channels.
> > + This driver supports SCSSI only.
> > +
> > + If your SoC supports SCSSI, say Y here.
> > +
> > config SPI_XCOMM
> > tristate "Analog Devices AD-FMCOMMS1-EBZ SPI-I2C-bridge driver"
> > depends on I2C
> > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index
> > cb1f437..a90d559 100644
> > --- a/drivers/spi/Makefile
> > +++ b/drivers/spi/Makefile
> > @@ -101,6 +101,7 @@ spi-thunderx-objs := spi-cavium.o
> > spi-cavium-thunderx.o
> > obj-$(CONFIG_SPI_THUNDERX) += spi-thunderx.o
> > obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
> > obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
> > +obj-$(CONFIG_SPI_UNIPHIER) += spi-uniphier.o
> > obj-$(CONFIG_SPI_XCOMM)+= spi-xcomm.o
> > obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
> > obj-$(CONFIG_SPI_XLP) += spi-xlp.o
> > diff --git a/drivers/spi/spi-uniphier.c b/drivers/spi/spi-uniphier.c
> > new file mode 100644 index 000..0899854
> > --- /dev/null
> > +++ b/drivers/spi/spi-uniphier.c
> > @@ -0,0 +1,525 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +// spi-uniphier.c - Socionext UniPhier SPI controller driver
> > +// Copyright 2012 Panasonic Corporation
> > +// Copyright 2016-2018 Socionext Inc.
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
>
> > +#include
> > +#include
>
> I fail to find where those two are used, just remove them.
I sent this modification as a new patch.
https://patchwork.kernel.org/patch/10553249/
> > +#include
> > +#include
> > +
> > +#include
> > +
> > +#define SSI_TIMEOUT_MS 2000
> > +#define SSI_MAX_CLK_DIVIDER254
> > +#define SSI_MIN_CLK_DIVIDER4
> > +
> > +struct uniphier_spi_priv {
> > + void __iomem *base;
> > + struct clk *clk;
> > + struct spi_master *master;
> > + struct completion xfer_done;
> > +
> > + int error;
> > + unsigned int tx_bytes;
> > + unsigned int rx_bytes;
> > + const u8 *tx_buf;
> > + u8 *rx_buf;
> > +
> > + bool is_save_param;
> > + u8 bits_per_word;
> > + u16 mode;
> > + u32 speed_hz;
> > +};
> > +
> > +#define SSI_CTL0x00
> > +#define SSI_CTL_EN
RE: [PATCH v3 2/2] spi: add SPI controller driver for UniPhier SoC
Hi Andy,
Thank you for your check.
> From: Andy Shevchenko [mailto:andy.shevche...@gmail.com]
> Sent: Wednesday, August 1, 2018 7:21 PM
> To: Hayashibara, Keiji/林原 啓二
> Subject: Re: [PATCH v3 2/2] spi: add SPI controller driver for UniPhier SoC
>
> On Wed, Aug 1, 2018 at 10:29 AM, Keiji Hayashibara
> wrote:
> > Add SPI controller driver implemented in Socionext UniPhier SoCs.
> >
> > UniPhier SoCs have two types SPI controllers; SCSSI supports a single
> > channel, and MCSSI supports multiple channels.
> > This driver supports SCSSI only.
> >
> > This controller has 32bit TX/RX FIFO with depth of eight entry, and
> > supports the SPI master mode only.
> >
> > This commit is implemented in PIO transfer mode, not DMA transfer.
> >
>
> One comment below, otherwise FWIW,
> Reviewed-by: Andy Shevchenko
>
>
> > Signed-off-by: Kunihiko Hayashi
> > Signed-off-by: Keiji Hayashibara
> > ---
> > drivers/spi/Kconfig| 13 ++
> > drivers/spi/Makefile | 1 +
> > drivers/spi/spi-uniphier.c | 525
> > +
> > 3 files changed, 539 insertions(+)
> > create mode 100644 drivers/spi/spi-uniphier.c
> >
> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index
> > ad5d68e..671d078 100644
> > --- a/drivers/spi/Kconfig
> > +++ b/drivers/spi/Kconfig
> > @@ -688,6 +688,19 @@ config SPI_TXX9
> > help
> > SPI driver for Toshiba TXx9 MIPS SoCs
> >
> > +config SPI_UNIPHIER
> > + tristate "Socionext UniPhier SPI Controller"
> > + depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
> > + help
> > + This enables a driver for the Socionext UniPhier SoC SCSSI SPI
> > controller.
> > +
> > + UniPhier SoCs have SCSSI and MCSSI SPI controllers.
> > + Every UniPhier SoC has SCSSI which supports single channel.
> > + Older UniPhier Pro4/Pro5 also has MCSSI which support multiple
> > channels.
> > + This driver supports SCSSI only.
> > +
> > + If your SoC supports SCSSI, say Y here.
> > +
> > config SPI_XCOMM
> > tristate "Analog Devices AD-FMCOMMS1-EBZ SPI-I2C-bridge driver"
> > depends on I2C
> > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index
> > cb1f437..a90d559 100644
> > --- a/drivers/spi/Makefile
> > +++ b/drivers/spi/Makefile
> > @@ -101,6 +101,7 @@ spi-thunderx-objs := spi-cavium.o
> > spi-cavium-thunderx.o
> > obj-$(CONFIG_SPI_THUNDERX) += spi-thunderx.o
> > obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
> > obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
> > +obj-$(CONFIG_SPI_UNIPHIER) += spi-uniphier.o
> > obj-$(CONFIG_SPI_XCOMM)+= spi-xcomm.o
> > obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
> > obj-$(CONFIG_SPI_XLP) += spi-xlp.o
> > diff --git a/drivers/spi/spi-uniphier.c b/drivers/spi/spi-uniphier.c
> > new file mode 100644 index 000..0899854
> > --- /dev/null
> > +++ b/drivers/spi/spi-uniphier.c
> > @@ -0,0 +1,525 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +// spi-uniphier.c - Socionext UniPhier SPI controller driver
> > +// Copyright 2012 Panasonic Corporation
> > +// Copyright 2016-2018 Socionext Inc.
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
>
> > +#include
> > +#include
>
> I fail to find where those two are used, just remove them.
I sent this modification as a new patch.
https://patchwork.kernel.org/patch/10553249/
> > +#include
> > +#include
> > +
> > +#include
> > +
> > +#define SSI_TIMEOUT_MS 2000
> > +#define SSI_MAX_CLK_DIVIDER254
> > +#define SSI_MIN_CLK_DIVIDER4
> > +
> > +struct uniphier_spi_priv {
> > + void __iomem *base;
> > + struct clk *clk;
> > + struct spi_master *master;
> > + struct completion xfer_done;
> > +
> > + int error;
> > + unsigned int tx_bytes;
> > + unsigned int rx_bytes;
> > + const u8 *tx_buf;
> > + u8 *rx_buf;
> > +
> > + bool is_save_param;
> > + u8 bits_per_word;
> > + u16 mode;
> > + u32 speed_hz;
> > +};
> > +
> > +#define SSI_CTL0x00
> > +#define SSI_CTL_EN
Re: [PATCH v3 2/2] spi: add SPI controller driver for UniPhier SoC
On Wed, Aug 1, 2018 at 10:29 AM, Keiji Hayashibara
wrote:
> Add SPI controller driver implemented in Socionext UniPhier SoCs.
>
> UniPhier SoCs have two types SPI controllers; SCSSI supports a
> single channel, and MCSSI supports multiple channels.
> This driver supports SCSSI only.
>
> This controller has 32bit TX/RX FIFO with depth of eight entry,
> and supports the SPI master mode only.
>
> This commit is implemented in PIO transfer mode, not DMA transfer.
>
One comment below, otherwise FWIW,
Reviewed-by: Andy Shevchenko
> Signed-off-by: Kunihiko Hayashi
> Signed-off-by: Keiji Hayashibara
> ---
> drivers/spi/Kconfig| 13 ++
> drivers/spi/Makefile | 1 +
> drivers/spi/spi-uniphier.c | 525
> +
> 3 files changed, 539 insertions(+)
> create mode 100644 drivers/spi/spi-uniphier.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index ad5d68e..671d078 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -688,6 +688,19 @@ config SPI_TXX9
> help
> SPI driver for Toshiba TXx9 MIPS SoCs
>
> +config SPI_UNIPHIER
> + tristate "Socionext UniPhier SPI Controller"
> + depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
> + help
> + This enables a driver for the Socionext UniPhier SoC SCSSI SPI
> controller.
> +
> + UniPhier SoCs have SCSSI and MCSSI SPI controllers.
> + Every UniPhier SoC has SCSSI which supports single channel.
> + Older UniPhier Pro4/Pro5 also has MCSSI which support multiple
> channels.
> + This driver supports SCSSI only.
> +
> + If your SoC supports SCSSI, say Y here.
> +
> config SPI_XCOMM
> tristate "Analog Devices AD-FMCOMMS1-EBZ SPI-I2C-bridge driver"
> depends on I2C
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index cb1f437..a90d559 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -101,6 +101,7 @@ spi-thunderx-objs := spi-cavium.o
> spi-cavium-thunderx.o
> obj-$(CONFIG_SPI_THUNDERX) += spi-thunderx.o
> obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
> obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
> +obj-$(CONFIG_SPI_UNIPHIER) += spi-uniphier.o
> obj-$(CONFIG_SPI_XCOMM)+= spi-xcomm.o
> obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
> obj-$(CONFIG_SPI_XLP) += spi-xlp.o
> diff --git a/drivers/spi/spi-uniphier.c b/drivers/spi/spi-uniphier.c
> new file mode 100644
> index 000..0899854
> --- /dev/null
> +++ b/drivers/spi/spi-uniphier.c
> @@ -0,0 +1,525 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// spi-uniphier.c - Socionext UniPhier SPI controller driver
> +// Copyright 2012 Panasonic Corporation
> +// Copyright 2016-2018 Socionext Inc.
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
I fail to find where those two are used, just remove them.
> +#include
> +#include
> +
> +#include
> +
> +#define SSI_TIMEOUT_MS 2000
> +#define SSI_MAX_CLK_DIVIDER254
> +#define SSI_MIN_CLK_DIVIDER4
> +
> +struct uniphier_spi_priv {
> + void __iomem *base;
> + struct clk *clk;
> + struct spi_master *master;
> + struct completion xfer_done;
> +
> + int error;
> + unsigned int tx_bytes;
> + unsigned int rx_bytes;
> + const u8 *tx_buf;
> + u8 *rx_buf;
> +
> + bool is_save_param;
> + u8 bits_per_word;
> + u16 mode;
> + u32 speed_hz;
> +};
> +
> +#define SSI_CTL0x00
> +#define SSI_CTL_EN BIT(0)
> +
> +#define SSI_CKS0x04
> +#define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
> +#define SSI_CKS_CKPHSBIT(14)
> +#define SSI_CKS_CKINIT BIT(13)
> +#define SSI_CKS_CKDLYBIT(12)
> +
> +#define SSI_TXWDS 0x08
> +#define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
> +#define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
> +#define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
> +
> +#define SSI_RXWDS 0x0c
> +#define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
> +
> +#define SSI_FPS0x10
> +#define SSI_FPS_FSPOLBIT(15)
> +#define SSI_FPS_FSTRTBIT(14)
> +
> +#define SSI_SR 0x14
> +#define SSI_SR_RNE BIT(0)
> +
> +#define SSI_IE 0x18
> +#define SSI_IE_RCIE BIT(3)
> +#define SSI_IE_RORIE BIT(0)
> +
> +#define SSI_IS 0x1c
> +#define SSI_IS_RXRS BIT(9)
> +#define SSI_IS_RCID BIT(3)
> +#define SSI_IS_RORID BIT(0)
> +
> +#define SSI_IC 0x1c
> +#define SSI_IC_TCIC BIT(4)
> +#define SSI_IC_RCIC BIT(3)
> +#define SSI_IC_RORIC BIT(0)
> +
> +#define SSI_FC 0x20
> +#define SSI_FC_TXFFL
Re: [PATCH v3 2/2] spi: add SPI controller driver for UniPhier SoC
On Wed, Aug 1, 2018 at 10:29 AM, Keiji Hayashibara
wrote:
> Add SPI controller driver implemented in Socionext UniPhier SoCs.
>
> UniPhier SoCs have two types SPI controllers; SCSSI supports a
> single channel, and MCSSI supports multiple channels.
> This driver supports SCSSI only.
>
> This controller has 32bit TX/RX FIFO with depth of eight entry,
> and supports the SPI master mode only.
>
> This commit is implemented in PIO transfer mode, not DMA transfer.
>
One comment below, otherwise FWIW,
Reviewed-by: Andy Shevchenko
> Signed-off-by: Kunihiko Hayashi
> Signed-off-by: Keiji Hayashibara
> ---
> drivers/spi/Kconfig| 13 ++
> drivers/spi/Makefile | 1 +
> drivers/spi/spi-uniphier.c | 525
> +
> 3 files changed, 539 insertions(+)
> create mode 100644 drivers/spi/spi-uniphier.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index ad5d68e..671d078 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -688,6 +688,19 @@ config SPI_TXX9
> help
> SPI driver for Toshiba TXx9 MIPS SoCs
>
> +config SPI_UNIPHIER
> + tristate "Socionext UniPhier SPI Controller"
> + depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
> + help
> + This enables a driver for the Socionext UniPhier SoC SCSSI SPI
> controller.
> +
> + UniPhier SoCs have SCSSI and MCSSI SPI controllers.
> + Every UniPhier SoC has SCSSI which supports single channel.
> + Older UniPhier Pro4/Pro5 also has MCSSI which support multiple
> channels.
> + This driver supports SCSSI only.
> +
> + If your SoC supports SCSSI, say Y here.
> +
> config SPI_XCOMM
> tristate "Analog Devices AD-FMCOMMS1-EBZ SPI-I2C-bridge driver"
> depends on I2C
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index cb1f437..a90d559 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -101,6 +101,7 @@ spi-thunderx-objs := spi-cavium.o
> spi-cavium-thunderx.o
> obj-$(CONFIG_SPI_THUNDERX) += spi-thunderx.o
> obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
> obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
> +obj-$(CONFIG_SPI_UNIPHIER) += spi-uniphier.o
> obj-$(CONFIG_SPI_XCOMM)+= spi-xcomm.o
> obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
> obj-$(CONFIG_SPI_XLP) += spi-xlp.o
> diff --git a/drivers/spi/spi-uniphier.c b/drivers/spi/spi-uniphier.c
> new file mode 100644
> index 000..0899854
> --- /dev/null
> +++ b/drivers/spi/spi-uniphier.c
> @@ -0,0 +1,525 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// spi-uniphier.c - Socionext UniPhier SPI controller driver
> +// Copyright 2012 Panasonic Corporation
> +// Copyright 2016-2018 Socionext Inc.
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
I fail to find where those two are used, just remove them.
> +#include
> +#include
> +
> +#include
> +
> +#define SSI_TIMEOUT_MS 2000
> +#define SSI_MAX_CLK_DIVIDER254
> +#define SSI_MIN_CLK_DIVIDER4
> +
> +struct uniphier_spi_priv {
> + void __iomem *base;
> + struct clk *clk;
> + struct spi_master *master;
> + struct completion xfer_done;
> +
> + int error;
> + unsigned int tx_bytes;
> + unsigned int rx_bytes;
> + const u8 *tx_buf;
> + u8 *rx_buf;
> +
> + bool is_save_param;
> + u8 bits_per_word;
> + u16 mode;
> + u32 speed_hz;
> +};
> +
> +#define SSI_CTL0x00
> +#define SSI_CTL_EN BIT(0)
> +
> +#define SSI_CKS0x04
> +#define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
> +#define SSI_CKS_CKPHSBIT(14)
> +#define SSI_CKS_CKINIT BIT(13)
> +#define SSI_CKS_CKDLYBIT(12)
> +
> +#define SSI_TXWDS 0x08
> +#define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
> +#define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
> +#define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
> +
> +#define SSI_RXWDS 0x0c
> +#define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
> +
> +#define SSI_FPS0x10
> +#define SSI_FPS_FSPOLBIT(15)
> +#define SSI_FPS_FSTRTBIT(14)
> +
> +#define SSI_SR 0x14
> +#define SSI_SR_RNE BIT(0)
> +
> +#define SSI_IE 0x18
> +#define SSI_IE_RCIE BIT(3)
> +#define SSI_IE_RORIE BIT(0)
> +
> +#define SSI_IS 0x1c
> +#define SSI_IS_RXRS BIT(9)
> +#define SSI_IS_RCID BIT(3)
> +#define SSI_IS_RORID BIT(0)
> +
> +#define SSI_IC 0x1c
> +#define SSI_IC_TCIC BIT(4)
> +#define SSI_IC_RCIC BIT(3)
> +#define SSI_IC_RORIC BIT(0)
> +
> +#define SSI_FC 0x20
> +#define SSI_FC_TXFFL
[PATCH v3 2/2] spi: add SPI controller driver for UniPhier SoC
Add SPI controller driver implemented in Socionext UniPhier SoCs.
UniPhier SoCs have two types SPI controllers; SCSSI supports a
single channel, and MCSSI supports multiple channels.
This driver supports SCSSI only.
This controller has 32bit TX/RX FIFO with depth of eight entry,
and supports the SPI master mode only.
This commit is implemented in PIO transfer mode, not DMA transfer.
Signed-off-by: Kunihiko Hayashi
Signed-off-by: Keiji Hayashibara
---
drivers/spi/Kconfig| 13 ++
drivers/spi/Makefile | 1 +
drivers/spi/spi-uniphier.c | 525 +
3 files changed, 539 insertions(+)
create mode 100644 drivers/spi/spi-uniphier.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ad5d68e..671d078 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -688,6 +688,19 @@ config SPI_TXX9
help
SPI driver for Toshiba TXx9 MIPS SoCs
+config SPI_UNIPHIER
+ tristate "Socionext UniPhier SPI Controller"
+ depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
+ help
+ This enables a driver for the Socionext UniPhier SoC SCSSI SPI
controller.
+
+ UniPhier SoCs have SCSSI and MCSSI SPI controllers.
+ Every UniPhier SoC has SCSSI which supports single channel.
+ Older UniPhier Pro4/Pro5 also has MCSSI which support multiple
channels.
+ This driver supports SCSSI only.
+
+ If your SoC supports SCSSI, say Y here.
+
config SPI_XCOMM
tristate "Analog Devices AD-FMCOMMS1-EBZ SPI-I2C-bridge driver"
depends on I2C
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index cb1f437..a90d559 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -101,6 +101,7 @@ spi-thunderx-objs := spi-cavium.o
spi-cavium-thunderx.o
obj-$(CONFIG_SPI_THUNDERX) += spi-thunderx.o
obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
+obj-$(CONFIG_SPI_UNIPHIER) += spi-uniphier.o
obj-$(CONFIG_SPI_XCOMM)+= spi-xcomm.o
obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
obj-$(CONFIG_SPI_XLP) += spi-xlp.o
diff --git a/drivers/spi/spi-uniphier.c b/drivers/spi/spi-uniphier.c
new file mode 100644
index 000..0899854
--- /dev/null
+++ b/drivers/spi/spi-uniphier.c
@@ -0,0 +1,525 @@
+// SPDX-License-Identifier: GPL-2.0
+// spi-uniphier.c - Socionext UniPhier SPI controller driver
+// Copyright 2012 Panasonic Corporation
+// Copyright 2016-2018 Socionext Inc.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define SSI_TIMEOUT_MS 2000
+#define SSI_MAX_CLK_DIVIDER254
+#define SSI_MIN_CLK_DIVIDER4
+
+struct uniphier_spi_priv {
+ void __iomem *base;
+ struct clk *clk;
+ struct spi_master *master;
+ struct completion xfer_done;
+
+ int error;
+ unsigned int tx_bytes;
+ unsigned int rx_bytes;
+ const u8 *tx_buf;
+ u8 *rx_buf;
+
+ bool is_save_param;
+ u8 bits_per_word;
+ u16 mode;
+ u32 speed_hz;
+};
+
+#define SSI_CTL0x00
+#define SSI_CTL_EN BIT(0)
+
+#define SSI_CKS0x04
+#define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
+#define SSI_CKS_CKPHSBIT(14)
+#define SSI_CKS_CKINIT BIT(13)
+#define SSI_CKS_CKDLYBIT(12)
+
+#define SSI_TXWDS 0x08
+#define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
+#define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
+#define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
+
+#define SSI_RXWDS 0x0c
+#define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
+
+#define SSI_FPS0x10
+#define SSI_FPS_FSPOLBIT(15)
+#define SSI_FPS_FSTRTBIT(14)
+
+#define SSI_SR 0x14
+#define SSI_SR_RNE BIT(0)
+
+#define SSI_IE 0x18
+#define SSI_IE_RCIE BIT(3)
+#define SSI_IE_RORIE BIT(0)
+
+#define SSI_IS 0x1c
+#define SSI_IS_RXRS BIT(9)
+#define SSI_IS_RCID BIT(3)
+#define SSI_IS_RORID BIT(0)
+
+#define SSI_IC 0x1c
+#define SSI_IC_TCIC BIT(4)
+#define SSI_IC_RCIC BIT(3)
+#define SSI_IC_RORIC BIT(0)
+
+#define SSI_FC 0x20
+#define SSI_FC_TXFFL BIT(12)
+#define SSI_FC_TXFTH_MASKGENMASK(11, 8)
+#define SSI_FC_RXFFL BIT(4)
+#define SSI_FC_RXFTH_MASKGENMASK(3, 0)
+
+#define SSI_TXDR 0x24
+#define SSI_RXDR 0x24
+
+#define SSI_FIFO_DEPTH 8U
+
+static inline unsigned int bytes_per_word(unsigned int bits)
+{
+ return bits <= 8 ? 1 : (bits <= 16 ? 2 : 4);
+}
+
+static inline void uniphier_spi_irq_enable(struct spi_device *spi, u32 mask)
+{
+ struct
[PATCH v3 2/2] spi: add SPI controller driver for UniPhier SoC
Add SPI controller driver implemented in Socionext UniPhier SoCs.
UniPhier SoCs have two types SPI controllers; SCSSI supports a
single channel, and MCSSI supports multiple channels.
This driver supports SCSSI only.
This controller has 32bit TX/RX FIFO with depth of eight entry,
and supports the SPI master mode only.
This commit is implemented in PIO transfer mode, not DMA transfer.
Signed-off-by: Kunihiko Hayashi
Signed-off-by: Keiji Hayashibara
---
drivers/spi/Kconfig| 13 ++
drivers/spi/Makefile | 1 +
drivers/spi/spi-uniphier.c | 525 +
3 files changed, 539 insertions(+)
create mode 100644 drivers/spi/spi-uniphier.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ad5d68e..671d078 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -688,6 +688,19 @@ config SPI_TXX9
help
SPI driver for Toshiba TXx9 MIPS SoCs
+config SPI_UNIPHIER
+ tristate "Socionext UniPhier SPI Controller"
+ depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
+ help
+ This enables a driver for the Socionext UniPhier SoC SCSSI SPI
controller.
+
+ UniPhier SoCs have SCSSI and MCSSI SPI controllers.
+ Every UniPhier SoC has SCSSI which supports single channel.
+ Older UniPhier Pro4/Pro5 also has MCSSI which support multiple
channels.
+ This driver supports SCSSI only.
+
+ If your SoC supports SCSSI, say Y here.
+
config SPI_XCOMM
tristate "Analog Devices AD-FMCOMMS1-EBZ SPI-I2C-bridge driver"
depends on I2C
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index cb1f437..a90d559 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -101,6 +101,7 @@ spi-thunderx-objs := spi-cavium.o
spi-cavium-thunderx.o
obj-$(CONFIG_SPI_THUNDERX) += spi-thunderx.o
obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
+obj-$(CONFIG_SPI_UNIPHIER) += spi-uniphier.o
obj-$(CONFIG_SPI_XCOMM)+= spi-xcomm.o
obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
obj-$(CONFIG_SPI_XLP) += spi-xlp.o
diff --git a/drivers/spi/spi-uniphier.c b/drivers/spi/spi-uniphier.c
new file mode 100644
index 000..0899854
--- /dev/null
+++ b/drivers/spi/spi-uniphier.c
@@ -0,0 +1,525 @@
+// SPDX-License-Identifier: GPL-2.0
+// spi-uniphier.c - Socionext UniPhier SPI controller driver
+// Copyright 2012 Panasonic Corporation
+// Copyright 2016-2018 Socionext Inc.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define SSI_TIMEOUT_MS 2000
+#define SSI_MAX_CLK_DIVIDER254
+#define SSI_MIN_CLK_DIVIDER4
+
+struct uniphier_spi_priv {
+ void __iomem *base;
+ struct clk *clk;
+ struct spi_master *master;
+ struct completion xfer_done;
+
+ int error;
+ unsigned int tx_bytes;
+ unsigned int rx_bytes;
+ const u8 *tx_buf;
+ u8 *rx_buf;
+
+ bool is_save_param;
+ u8 bits_per_word;
+ u16 mode;
+ u32 speed_hz;
+};
+
+#define SSI_CTL0x00
+#define SSI_CTL_EN BIT(0)
+
+#define SSI_CKS0x04
+#define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
+#define SSI_CKS_CKPHSBIT(14)
+#define SSI_CKS_CKINIT BIT(13)
+#define SSI_CKS_CKDLYBIT(12)
+
+#define SSI_TXWDS 0x08
+#define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
+#define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
+#define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
+
+#define SSI_RXWDS 0x0c
+#define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
+
+#define SSI_FPS0x10
+#define SSI_FPS_FSPOLBIT(15)
+#define SSI_FPS_FSTRTBIT(14)
+
+#define SSI_SR 0x14
+#define SSI_SR_RNE BIT(0)
+
+#define SSI_IE 0x18
+#define SSI_IE_RCIE BIT(3)
+#define SSI_IE_RORIE BIT(0)
+
+#define SSI_IS 0x1c
+#define SSI_IS_RXRS BIT(9)
+#define SSI_IS_RCID BIT(3)
+#define SSI_IS_RORID BIT(0)
+
+#define SSI_IC 0x1c
+#define SSI_IC_TCIC BIT(4)
+#define SSI_IC_RCIC BIT(3)
+#define SSI_IC_RORIC BIT(0)
+
+#define SSI_FC 0x20
+#define SSI_FC_TXFFL BIT(12)
+#define SSI_FC_TXFTH_MASKGENMASK(11, 8)
+#define SSI_FC_RXFFL BIT(4)
+#define SSI_FC_RXFTH_MASKGENMASK(3, 0)
+
+#define SSI_TXDR 0x24
+#define SSI_RXDR 0x24
+
+#define SSI_FIFO_DEPTH 8U
+
+static inline unsigned int bytes_per_word(unsigned int bits)
+{
+ return bits <= 8 ? 1 : (bits <= 16 ? 2 : 4);
+}
+
+static inline void uniphier_spi_irq_enable(struct spi_device *spi, u32 mask)
+{
+ struct
