Re: [PATCH v4 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 9/11/2018 4:15 AM, vnkgu...@codeaurora.org wrote:
On 2018-09-06 22:02, Sai Prakash Ranjan wrote:
On 9/7/2018 4:01 AM, vnkgu...@codeaurora.org wrote:
On 2018-09-06 05:38, Sai Prakash Ranjan wrote:
On 9/5/2018 4:52 AM, Venkata Narendra Kumar Gutta wrote:
+static const struct of_device_id qcom_llcc_edac_match_table[] = {
+ { .compatible = "qcom,llcc-edac" },
+ { },
+};
+
Hi Venkata,
Devicetree binding for llcc is updated, but what about this compatible?
Does it need documentation too? I was not sure if I should add
documentation for this or not!
It does not require a separate binding, what I meant was to add this
compatible in the llcc binding itself, maybe as a subnode if it is
correct.
Hi,
We aren't really using this of_device_id structure, as this driver is
being registered from LLCC through
platform_register_device_data(...). This structure initialization is
just dead code as this driver won't be probed based on the DT entries.
Hence removing this compatible property and the corresponding struct in
the next patchset.
So, this doesn't need an extra binding/documentation.
Ok. Now that you have removed the compatible, it should be fine.
Thanks
Re: [PATCH v4 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 9/11/2018 4:15 AM, vnkgu...@codeaurora.org wrote:
On 2018-09-06 22:02, Sai Prakash Ranjan wrote:
On 9/7/2018 4:01 AM, vnkgu...@codeaurora.org wrote:
On 2018-09-06 05:38, Sai Prakash Ranjan wrote:
On 9/5/2018 4:52 AM, Venkata Narendra Kumar Gutta wrote:
+static const struct of_device_id qcom_llcc_edac_match_table[] = {
+ { .compatible = "qcom,llcc-edac" },
+ { },
+};
+
Hi Venkata,
Devicetree binding for llcc is updated, but what about this compatible?
Does it need documentation too? I was not sure if I should add
documentation for this or not!
It does not require a separate binding, what I meant was to add this
compatible in the llcc binding itself, maybe as a subnode if it is
correct.
Hi,
We aren't really using this of_device_id structure, as this driver is
being registered from LLCC through
platform_register_device_data(...). This structure initialization is
just dead code as this driver won't be probed based on the DT entries.
Hence removing this compatible property and the corresponding struct in
the next patchset.
So, this doesn't need an extra binding/documentation.
Ok. Now that you have removed the compatible, it should be fine.
Thanks
Re: [PATCH v4 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 2018-09-06 22:02, Sai Prakash Ranjan wrote:
On 9/7/2018 4:01 AM, vnkgu...@codeaurora.org wrote:
On 2018-09-06 05:38, Sai Prakash Ranjan wrote:
On 9/5/2018 4:52 AM, Venkata Narendra Kumar Gutta wrote:
+static const struct of_device_id qcom_llcc_edac_match_table[] = {
+ { .compatible = "qcom,llcc-edac" },
+ { },
+};
+
Hi Venkata,
Devicetree binding for llcc is updated, but what about this
compatible?
Does it need documentation too? I was not sure if I should add
documentation for this or not!
It does not require a separate binding, what I meant was to add this
compatible in the llcc binding itself, maybe as a subnode if it is
correct.
Hi,
We aren't really using this of_device_id structure, as this driver is
being registered from LLCC through
platform_register_device_data(...). This structure initialization is
just dead code as this driver won't be probed based on the DT entries.
Hence removing this compatible property and the corresponding struct in
the next patchset.
So, this doesn't need an extra binding/documentation.
Re: [PATCH v4 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 2018-09-06 22:02, Sai Prakash Ranjan wrote:
On 9/7/2018 4:01 AM, vnkgu...@codeaurora.org wrote:
On 2018-09-06 05:38, Sai Prakash Ranjan wrote:
On 9/5/2018 4:52 AM, Venkata Narendra Kumar Gutta wrote:
+static const struct of_device_id qcom_llcc_edac_match_table[] = {
+ { .compatible = "qcom,llcc-edac" },
+ { },
+};
+
Hi Venkata,
Devicetree binding for llcc is updated, but what about this
compatible?
Does it need documentation too? I was not sure if I should add
documentation for this or not!
It does not require a separate binding, what I meant was to add this
compatible in the llcc binding itself, maybe as a subnode if it is
correct.
Hi,
We aren't really using this of_device_id structure, as this driver is
being registered from LLCC through
platform_register_device_data(...). This structure initialization is
just dead code as this driver won't be probed based on the DT entries.
Hence removing this compatible property and the corresponding struct in
the next patchset.
So, this doesn't need an extra binding/documentation.
Re: [PATCH v4 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On Tue, Sep 04, 2018 at 04:22:24PM -0700, Venkata Narendra Kumar Gutta wrote: > From: Channagoud Kadabi > > Add error reporting driver for Single Bit Errors (SBEs) and Double Bit > Errors (DBEs). As of now, this driver supports error reporting for > Last Level Cache Controller (LLCC) of Tag RAM and Data RAM. Interrupts > are triggered when the errors happen in the cache, the driver handles > those interrupts and dumps the syndrome registers. > > Signed-off-by: Channagoud Kadabi > Signed-off-by: Venkata Narendra Kumar Gutta > Co-developed-by: Venkata Narendra Kumar Gutta > --- > MAINTAINERS| 8 + > drivers/edac/Kconfig | 14 ++ > drivers/edac/Makefile | 1 + > drivers/edac/qcom_edac.c | 420 > + > include/linux/soc/qcom/llcc-qcom.h | 24 +++ > 5 files changed, 467 insertions(+) > create mode 100644 drivers/edac/qcom_edac.c EDAC bits look ok now, feel free to carry it through the qualcomm tree: Acked-by: Borislav Petkov -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.
Re: [PATCH v4 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On Tue, Sep 04, 2018 at 04:22:24PM -0700, Venkata Narendra Kumar Gutta wrote: > From: Channagoud Kadabi > > Add error reporting driver for Single Bit Errors (SBEs) and Double Bit > Errors (DBEs). As of now, this driver supports error reporting for > Last Level Cache Controller (LLCC) of Tag RAM and Data RAM. Interrupts > are triggered when the errors happen in the cache, the driver handles > those interrupts and dumps the syndrome registers. > > Signed-off-by: Channagoud Kadabi > Signed-off-by: Venkata Narendra Kumar Gutta > Co-developed-by: Venkata Narendra Kumar Gutta > --- > MAINTAINERS| 8 + > drivers/edac/Kconfig | 14 ++ > drivers/edac/Makefile | 1 + > drivers/edac/qcom_edac.c | 420 > + > include/linux/soc/qcom/llcc-qcom.h | 24 +++ > 5 files changed, 467 insertions(+) > create mode 100644 drivers/edac/qcom_edac.c EDAC bits look ok now, feel free to carry it through the qualcomm tree: Acked-by: Borislav Petkov -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.
Re: [PATCH v4 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 9/7/2018 4:01 AM, vnkgu...@codeaurora.org wrote:
On 2018-09-06 05:38, Sai Prakash Ranjan wrote:
On 9/5/2018 4:52 AM, Venkata Narendra Kumar Gutta wrote:
+static const struct of_device_id qcom_llcc_edac_match_table[] = {
+ { .compatible = "qcom,llcc-edac" },
+ { },
+};
+
Hi Venkata,
Devicetree binding for llcc is updated, but what about this compatible?
Does it need documentation too? I was not sure if I should add
documentation for this or not!
It does not require a separate binding, what I meant was to add this
compatible in the llcc binding itself, maybe as a subnode if it is correct.
Re: [PATCH v4 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 9/7/2018 4:01 AM, vnkgu...@codeaurora.org wrote:
On 2018-09-06 05:38, Sai Prakash Ranjan wrote:
On 9/5/2018 4:52 AM, Venkata Narendra Kumar Gutta wrote:
+static const struct of_device_id qcom_llcc_edac_match_table[] = {
+ { .compatible = "qcom,llcc-edac" },
+ { },
+};
+
Hi Venkata,
Devicetree binding for llcc is updated, but what about this compatible?
Does it need documentation too? I was not sure if I should add
documentation for this or not!
It does not require a separate binding, what I meant was to add this
compatible in the llcc binding itself, maybe as a subnode if it is correct.
Re: [PATCH v4 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 2018-09-06 05:38, Sai Prakash Ranjan wrote:
On 9/5/2018 4:52 AM, Venkata Narendra Kumar Gutta wrote:
+static const struct of_device_id qcom_llcc_edac_match_table[] = {
+ { .compatible = "qcom,llcc-edac" },
+ { },
+};
+
Hi Venkata,
Devicetree binding for llcc is updated, but what about this compatible?
Does it need documentation too? I was not sure if I should add
documentation for this or not!
Regards,
Sai
Re: [PATCH v4 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 2018-09-06 05:38, Sai Prakash Ranjan wrote:
On 9/5/2018 4:52 AM, Venkata Narendra Kumar Gutta wrote:
+static const struct of_device_id qcom_llcc_edac_match_table[] = {
+ { .compatible = "qcom,llcc-edac" },
+ { },
+};
+
Hi Venkata,
Devicetree binding for llcc is updated, but what about this compatible?
Does it need documentation too? I was not sure if I should add
documentation for this or not!
Regards,
Sai
Re: [PATCH v4 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 9/5/2018 4:52 AM, Venkata Narendra Kumar Gutta wrote:
+static const struct of_device_id qcom_llcc_edac_match_table[] = {
+ { .compatible = "qcom,llcc-edac" },
+ { },
+};
+
Hi Venkata,
Devicetree binding for llcc is updated, but what about this compatible?
Regards,
Sai
Re: [PATCH v4 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
On 9/5/2018 4:52 AM, Venkata Narendra Kumar Gutta wrote:
+static const struct of_device_id qcom_llcc_edac_match_table[] = {
+ { .compatible = "qcom,llcc-edac" },
+ { },
+};
+
Hi Venkata,
Devicetree binding for llcc is updated, but what about this compatible?
Regards,
Sai
[PATCH v4 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
From: Channagoud Kadabi Add error reporting driver for Single Bit Errors (SBEs) and Double Bit Errors (DBEs). As of now, this driver supports error reporting for Last Level Cache Controller (LLCC) of Tag RAM and Data RAM. Interrupts are triggered when the errors happen in the cache, the driver handles those interrupts and dumps the syndrome registers. Signed-off-by: Channagoud Kadabi Signed-off-by: Venkata Narendra Kumar Gutta Co-developed-by: Venkata Narendra Kumar Gutta --- MAINTAINERS| 8 + drivers/edac/Kconfig | 14 ++ drivers/edac/Makefile | 1 + drivers/edac/qcom_edac.c | 420 + include/linux/soc/qcom/llcc-qcom.h | 24 +++ 5 files changed, 467 insertions(+) create mode 100644 drivers/edac/qcom_edac.c diff --git a/MAINTAINERS b/MAINTAINERS index 0a23427..0bff713 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5227,6 +5227,14 @@ L: linux-e...@vger.kernel.org S: Maintained F: drivers/edac/ti_edac.c +EDAC-QUALCOMM +M: Channagoud Kadabi +M: Venkata Narendra Kumar Gutta +L: linux-arm-...@vger.kernel.org +L: linux-e...@vger.kernel.org +S: Maintained +F: drivers/edac/qcom_edac.c + EDIROL UA-101/UA-1000 DRIVER M: Clemens Ladisch L: alsa-de...@alsa-project.org (moderated for non-subscribers) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 57304b2..c4e3472 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -460,4 +460,18 @@ config EDAC_TI Support for error detection and correction on the TI SoCs. +config EDAC_QCOM + tristate "QCOM EDAC Controller" + depends on ARCH_QCOM && QCOM_LLCC + help + Support for error detection and correction on the + QCOM SoCs. + + This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs). + As of now, it supports error reporting for Last Level Cache Controller (LLCC) + of Tag RAM and Data RAM. + + For debugging issues having to do with stability and overall system + health, you should probably say 'Y' here. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 02b43a7..716096d 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o obj-$(CONFIG_EDAC_SYNOPSYS)+= synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o obj-$(CONFIG_EDAC_TI) += ti_edac.o +obj-$(CONFIG_EDAC_QCOM)+= qcom_edac.o diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c new file mode 100644 index 000..1773216 --- /dev/null +++ b/drivers/edac/qcom_edac.c @@ -0,0 +1,420 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "edac_mc.h" +#include "edac_device.h" + +#define EDAC_LLCC "qcom_llcc" + +#define LLCC_ERP_PANIC_ON_UE1 + +#define TRP_SYN_REG_CNT 6 +#define DRP_SYN_REG_CNT 8 + +#define LLCC_COMMON_STATUS0 0x0003000c +#define LLCC_LB_CNT_MASKGENMASK(31, 28) +#define LLCC_LB_CNT_SHIFT 28 + +/* Single & double bit syndrome register offsets */ +#define TRP_ECC_SB_ERR_SYN0 0x0002304c +#define TRP_ECC_DB_ERR_SYN0 0x00020370 +#define DRP_ECC_SB_ERR_SYN0 0x0004204c +#define DRP_ECC_DB_ERR_SYN0 0x00042070 + +/* Error register offsets */ +#define TRP_ECC_ERROR_STATUS1 0x00020348 +#define TRP_ECC_ERROR_STATUS0 0x00020344 +#define DRP_ECC_ERROR_STATUS1 0x00042048 +#define DRP_ECC_ERROR_STATUS0 0x00042044 + +/* TRP, DRP interrupt register offsets */ +#define DRP_INTERRUPT_STATUS0x00041000 +#define TRP_INTERRUPT_0_STATUS 0x00020480 +#define DRP_INTERRUPT_CLEAR 0x00041008 +#define DRP_ECC_ERROR_CNTR_CLEAR0x00040004 +#define TRP_INTERRUPT_0_CLEAR 0x00020484 +#define TRP_ECC_ERROR_CNTR_CLEAR0x00020440 + +/* Mask and shift macros */ +#define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0) +#define ECC_DB_ERR_WAYS_MASKGENMASK(31, 16) +#define ECC_DB_ERR_WAYS_SHIFT BIT(4) + +#define ECC_SB_ERR_COUNT_MASK GENMASK(23, 16) +#define ECC_SB_ERR_COUNT_SHIFT BIT(4) +#define ECC_SB_ERR_WAYS_MASKGENMASK(15, 0) + +#define SB_ECC_ERRORBIT(0) +#define DB_ECC_ERRORBIT(1) + +#define DRP_TRP_INT_CLEAR GENMASK(1, 0) +#define DRP_TRP_CNT_CLEAR GENMASK(1, 0) + +/* Config registers offsets*/ +#define DRP_ECC_ERROR_CFG 0x0004 + +/* Tag RAM, Data RAM interrupt register offsets */ +#define CMN_INTERRUPT_0_ENABLE
[PATCH v4 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
From: Channagoud Kadabi Add error reporting driver for Single Bit Errors (SBEs) and Double Bit Errors (DBEs). As of now, this driver supports error reporting for Last Level Cache Controller (LLCC) of Tag RAM and Data RAM. Interrupts are triggered when the errors happen in the cache, the driver handles those interrupts and dumps the syndrome registers. Signed-off-by: Channagoud Kadabi Signed-off-by: Venkata Narendra Kumar Gutta Co-developed-by: Venkata Narendra Kumar Gutta --- MAINTAINERS| 8 + drivers/edac/Kconfig | 14 ++ drivers/edac/Makefile | 1 + drivers/edac/qcom_edac.c | 420 + include/linux/soc/qcom/llcc-qcom.h | 24 +++ 5 files changed, 467 insertions(+) create mode 100644 drivers/edac/qcom_edac.c diff --git a/MAINTAINERS b/MAINTAINERS index 0a23427..0bff713 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5227,6 +5227,14 @@ L: linux-e...@vger.kernel.org S: Maintained F: drivers/edac/ti_edac.c +EDAC-QUALCOMM +M: Channagoud Kadabi +M: Venkata Narendra Kumar Gutta +L: linux-arm-...@vger.kernel.org +L: linux-e...@vger.kernel.org +S: Maintained +F: drivers/edac/qcom_edac.c + EDIROL UA-101/UA-1000 DRIVER M: Clemens Ladisch L: alsa-de...@alsa-project.org (moderated for non-subscribers) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 57304b2..c4e3472 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -460,4 +460,18 @@ config EDAC_TI Support for error detection and correction on the TI SoCs. +config EDAC_QCOM + tristate "QCOM EDAC Controller" + depends on ARCH_QCOM && QCOM_LLCC + help + Support for error detection and correction on the + QCOM SoCs. + + This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs). + As of now, it supports error reporting for Last Level Cache Controller (LLCC) + of Tag RAM and Data RAM. + + For debugging issues having to do with stability and overall system + health, you should probably say 'Y' here. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 02b43a7..716096d 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o obj-$(CONFIG_EDAC_SYNOPSYS)+= synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o obj-$(CONFIG_EDAC_TI) += ti_edac.o +obj-$(CONFIG_EDAC_QCOM)+= qcom_edac.o diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c new file mode 100644 index 000..1773216 --- /dev/null +++ b/drivers/edac/qcom_edac.c @@ -0,0 +1,420 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "edac_mc.h" +#include "edac_device.h" + +#define EDAC_LLCC "qcom_llcc" + +#define LLCC_ERP_PANIC_ON_UE1 + +#define TRP_SYN_REG_CNT 6 +#define DRP_SYN_REG_CNT 8 + +#define LLCC_COMMON_STATUS0 0x0003000c +#define LLCC_LB_CNT_MASKGENMASK(31, 28) +#define LLCC_LB_CNT_SHIFT 28 + +/* Single & double bit syndrome register offsets */ +#define TRP_ECC_SB_ERR_SYN0 0x0002304c +#define TRP_ECC_DB_ERR_SYN0 0x00020370 +#define DRP_ECC_SB_ERR_SYN0 0x0004204c +#define DRP_ECC_DB_ERR_SYN0 0x00042070 + +/* Error register offsets */ +#define TRP_ECC_ERROR_STATUS1 0x00020348 +#define TRP_ECC_ERROR_STATUS0 0x00020344 +#define DRP_ECC_ERROR_STATUS1 0x00042048 +#define DRP_ECC_ERROR_STATUS0 0x00042044 + +/* TRP, DRP interrupt register offsets */ +#define DRP_INTERRUPT_STATUS0x00041000 +#define TRP_INTERRUPT_0_STATUS 0x00020480 +#define DRP_INTERRUPT_CLEAR 0x00041008 +#define DRP_ECC_ERROR_CNTR_CLEAR0x00040004 +#define TRP_INTERRUPT_0_CLEAR 0x00020484 +#define TRP_ECC_ERROR_CNTR_CLEAR0x00020440 + +/* Mask and shift macros */ +#define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0) +#define ECC_DB_ERR_WAYS_MASKGENMASK(31, 16) +#define ECC_DB_ERR_WAYS_SHIFT BIT(4) + +#define ECC_SB_ERR_COUNT_MASK GENMASK(23, 16) +#define ECC_SB_ERR_COUNT_SHIFT BIT(4) +#define ECC_SB_ERR_WAYS_MASKGENMASK(15, 0) + +#define SB_ECC_ERRORBIT(0) +#define DB_ECC_ERRORBIT(1) + +#define DRP_TRP_INT_CLEAR GENMASK(1, 0) +#define DRP_TRP_CNT_CLEAR GENMASK(1, 0) + +/* Config registers offsets*/ +#define DRP_ECC_ERROR_CFG 0x0004 + +/* Tag RAM, Data RAM interrupt register offsets */ +#define CMN_INTERRUPT_0_ENABLE
