Re: [PATCH v5] powerpc/rcpm: add RCPM driver
On Tue, Aug 4, 2015 at 4:23 AM, Scott Wood
wrote:
On Mon, 2015-08-03 at 19:14 +0800, Chenhui Zhao wrote:
On Sat, Aug 1, 2015 at 8:45 AM, Scott Wood
wrote:
> On Fri, 2015-06-26 at 15:44 +0800,
Yuantian.Tang@freescale.comwrote:
> > +static void rcpm_v1_set_ip_power(bool enable, u32 *mask)
> > +{
> > + if (enable)
> > + setbits32(_v1_regs->ippdexpcr, *mask);
> > + else
> > + clrbits32(_v1_regs->ippdexpcr, *mask);
> > +}
> > +
> > +static void rcpm_v2_set_ip_power(bool enable, u32 *mask)
> > +{
> > + if (enable)
> > + setbits32(_v2_regs->ippdexpcr[0], *mask);
> > + else
> > + clrbits32(_v2_regs->ippdexpcr[0], *mask);
> > +}
>
> Why do these take "u32 *mask" instead of "u32 mask"?
>
> -Scott
I think it can be used in the case where there are several mask
values.
When would that be?
-Scott
So far, only use one register, even though the register name is
"IPPDEXPCRn" (has "n" suffix) in T4 RM.
OK. Just change the parameter to "u32 mask".
-Chenhui
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Re: [PATCH v5] powerpc/rcpm: add RCPM driver
On Mon, 2015-08-03 at 19:14 +0800, Chenhui Zhao wrote:
> On Sat, Aug 1, 2015 at 8:45 AM, Scott Wood
> wrote:
> > On Fri, 2015-06-26 at 15:44 +0800, Yuantian.Tang@freescale.comwrote:
> > > +static void rcpm_v1_set_ip_power(bool enable, u32 *mask)
> > > +{
> > > + if (enable)
> > > + setbits32(_v1_regs->ippdexpcr, *mask);
> > > + else
> > > + clrbits32(_v1_regs->ippdexpcr, *mask);
> > > +}
> > > +
> > > +static void rcpm_v2_set_ip_power(bool enable, u32 *mask)
> > > +{
> > > + if (enable)
> > > + setbits32(_v2_regs->ippdexpcr[0], *mask);
> > > + else
> > > + clrbits32(_v2_regs->ippdexpcr[0], *mask);
> > > +}
> >
> > Why do these take "u32 *mask" instead of "u32 mask"?
> >
> > -Scott
>
> I think it can be used in the case where there are several mask values.
When would that be?
-Scott
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Re: [PATCH v5] powerpc/rcpm: add RCPM driver
On Sat, Aug 1, 2015 at 8:45 AM, Scott Wood
wrote:
On Fri, 2015-06-26 at 15:44 +0800, yuantian.t...@freescale.com wrote:
+static void rcpm_v1_set_ip_power(bool enable, u32 *mask)
+{
+ if (enable)
+ setbits32(_v1_regs->ippdexpcr, *mask);
+ else
+ clrbits32(_v1_regs->ippdexpcr, *mask);
+}
+
+static void rcpm_v2_set_ip_power(bool enable, u32 *mask)
+{
+ if (enable)
+ setbits32(_v2_regs->ippdexpcr[0], *mask);
+ else
+ clrbits32(_v2_regs->ippdexpcr[0], *mask);
+}
Why do these take "u32 *mask" instead of "u32 mask"?
-Scott
I think it can be used in the case where there are several mask values.
-Chenhui
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Re: [PATCH v5] powerpc/rcpm: add RCPM driver
On Tue, Aug 4, 2015 at 4:23 AM, Scott Wood scottw...@freescale.com
wrote:
On Mon, 2015-08-03 at 19:14 +0800, Chenhui Zhao wrote:
On Sat, Aug 1, 2015 at 8:45 AM, Scott Wood scottw...@freescale.com
wrote:
On Fri, 2015-06-26 at 15:44 +0800,
Yuantian.Tang@freescale.comwrote:
+static void rcpm_v1_set_ip_power(bool enable, u32 *mask)
+{
+ if (enable)
+ setbits32(rcpm_v1_regs-ippdexpcr, *mask);
+ else
+ clrbits32(rcpm_v1_regs-ippdexpcr, *mask);
+}
+
+static void rcpm_v2_set_ip_power(bool enable, u32 *mask)
+{
+ if (enable)
+ setbits32(rcpm_v2_regs-ippdexpcr[0], *mask);
+ else
+ clrbits32(rcpm_v2_regs-ippdexpcr[0], *mask);
+}
Why do these take u32 *mask instead of u32 mask?
-Scott
I think it can be used in the case where there are several mask
values.
When would that be?
-Scott
So far, only use one register, even though the register name is
IPPDEXPCRn (has n suffix) in T4 RM.
OK. Just change the parameter to u32 mask.
-Chenhui
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Re: [PATCH v5] powerpc/rcpm: add RCPM driver
On Sat, Aug 1, 2015 at 8:45 AM, Scott Wood scottw...@freescale.com
wrote:
On Fri, 2015-06-26 at 15:44 +0800, yuantian.t...@freescale.com wrote:
+static void rcpm_v1_set_ip_power(bool enable, u32 *mask)
+{
+ if (enable)
+ setbits32(rcpm_v1_regs-ippdexpcr, *mask);
+ else
+ clrbits32(rcpm_v1_regs-ippdexpcr, *mask);
+}
+
+static void rcpm_v2_set_ip_power(bool enable, u32 *mask)
+{
+ if (enable)
+ setbits32(rcpm_v2_regs-ippdexpcr[0], *mask);
+ else
+ clrbits32(rcpm_v2_regs-ippdexpcr[0], *mask);
+}
Why do these take u32 *mask instead of u32 mask?
-Scott
I think it can be used in the case where there are several mask values.
-Chenhui
--
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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5] powerpc/rcpm: add RCPM driver
On Mon, 2015-08-03 at 19:14 +0800, Chenhui Zhao wrote:
On Sat, Aug 1, 2015 at 8:45 AM, Scott Wood scottw...@freescale.com
wrote:
On Fri, 2015-06-26 at 15:44 +0800, Yuantian.Tang@freescale.comwrote:
+static void rcpm_v1_set_ip_power(bool enable, u32 *mask)
+{
+ if (enable)
+ setbits32(rcpm_v1_regs-ippdexpcr, *mask);
+ else
+ clrbits32(rcpm_v1_regs-ippdexpcr, *mask);
+}
+
+static void rcpm_v2_set_ip_power(bool enable, u32 *mask)
+{
+ if (enable)
+ setbits32(rcpm_v2_regs-ippdexpcr[0], *mask);
+ else
+ clrbits32(rcpm_v2_regs-ippdexpcr[0], *mask);
+}
Why do these take u32 *mask instead of u32 mask?
-Scott
I think it can be used in the case where there are several mask values.
When would that be?
-Scott
--
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Re: [PATCH v5] powerpc/rcpm: add RCPM driver
On Fri, 2015-06-26 at 15:44 +0800, yuantian.t...@freescale.com wrote:
> +static void rcpm_v1_set_ip_power(bool enable, u32 *mask)
> +{
> + if (enable)
> + setbits32(_v1_regs->ippdexpcr, *mask);
> + else
> + clrbits32(_v1_regs->ippdexpcr, *mask);
> +}
> +
> +static void rcpm_v2_set_ip_power(bool enable, u32 *mask)
> +{
> + if (enable)
> + setbits32(_v2_regs->ippdexpcr[0], *mask);
> + else
> + clrbits32(_v2_regs->ippdexpcr[0], *mask);
> +}
Why do these take "u32 *mask" instead of "u32 mask"?
-Scott
--
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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5] powerpc/rcpm: add RCPM driver
On Fri, 2015-06-26 at 15:44 +0800, yuantian.t...@freescale.com wrote:
+static void rcpm_v1_set_ip_power(bool enable, u32 *mask)
+{
+ if (enable)
+ setbits32(rcpm_v1_regs-ippdexpcr, *mask);
+ else
+ clrbits32(rcpm_v1_regs-ippdexpcr, *mask);
+}
+
+static void rcpm_v2_set_ip_power(bool enable, u32 *mask)
+{
+ if (enable)
+ setbits32(rcpm_v2_regs-ippdexpcr[0], *mask);
+ else
+ clrbits32(rcpm_v2_regs-ippdexpcr[0], *mask);
+}
Why do these take u32 *mask instead of u32 mask?
-Scott
--
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[PATCH v5] powerpc/rcpm: add RCPM driver
From: Tang Yuantian
There is a RCPM (Run Control/Power Management) in Freescale QorIQ
series processors. The device performs tasks associated with device
run control and power management.
The driver implements some features: mask/unmask irq, enter/exit low
power states, freeze time base, etc.
Signed-off-by: Chenhui Zhao
Signed-off-by: Tang Yuantian
---
v5:
- update chassis version for t1040 in bindings
v4:
- refine bindings document
v3:
- added static and __init modifier to fsl_rcpm_init
v2:
- fix code style issues
- refine compatible string match part
Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 44 +++
arch/powerpc/include/asm/fsl_guts.h| 105 +++
arch/powerpc/include/asm/fsl_pm.h | 48 +++
arch/powerpc/platforms/85xx/Kconfig| 1 +
arch/powerpc/sysdev/Kconfig| 5 +
arch/powerpc/sysdev/Makefile | 1 +
arch/powerpc/sysdev/fsl_rcpm.c | 338 +
7 files changed, 542 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/fsl/rcpm.txt
create mode 100644 arch/powerpc/include/asm/fsl_pm.h
create mode 100644 arch/powerpc/sysdev/fsl_rcpm.c
diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
new file mode 100644
index 000..dc52f70
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
@@ -0,0 +1,44 @@
+* Run Control and Power Management
+
+The RCPM performs all device-level tasks associated with device run control
+and power management.
+
+Required properites:
+ - reg : Offset and length of the register set of RCPM block.
+ - compatible : Sould contain a chip-specific RCPM block compatible string
+ and (if applicable) may contain a chassis-version RCPM compatible
string.
+ Chip-specific strings are of the form "fsl,-rcpm", such as:
+ * "fsl,p2041-rcpm"
+ * "fsl,p3041-rcpm"
+ * "fsl,p4080-rcpm"
+ * "fsl,p5020-rcpm"
+ * "fsl,p5040-rcpm"
+ * "fsl,t4240-rcpm"
+ * "fsl,b4420-rcpm"
+ * "fsl,b4860-rcpm"
+
+ Chassis-version RCPM strings include:
+ * "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm
+ * "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm
+ * "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm
+
+All references to "1.0" and "2.0" refer to the QorIQ chassis version to
+which the chip complies.
+Chassis VersionExample Chips
+------
+1.0p4080, p5020, p5040, p2041, p3041
+2.0t4240, b4860, b4420
+2.1t1040
+
+Example:
+The RCPM node for T4240:
+ rcpm: global-utilities@e2000 {
+ compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
+ reg = <0xe2000 0x1000>;
+ };
+
+The RCPM node for P4080:
+ rcpm: global-utilities@e2000 {
+ compatible = "fsl,qoriq-rcpm-1.0";
+ reg = <0xe2000 0x1000>;
+ };
diff --git a/arch/powerpc/include/asm/fsl_guts.h
b/arch/powerpc/include/asm/fsl_guts.h
index 43b6bb1..a67413c 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -188,5 +188,110 @@ static inline void guts_set_pmuxcr_dma(struct ccsr_guts
__iomem *guts,
#endif
+struct ccsr_rcpm_v1 {
+ u8 res[4];
+ __be32 cdozsr; /* 0x0004 Core Doze Status Register */
+ u8 res0008[4];
+ __be32 cdozcr; /* 0x000c Core Doze Control Register */
+ u8 res0010[4];
+ __be32 cnapsr; /* 0x0014 Core Nap Status Register */
+ u8 res0018[4];
+ __be32 cnapcr; /* 0x001c Core Nap Control Register */
+ u8 res0020[4];
+ __be32 cdozpsr;/* 0x0024 Core Doze Previous Status Register */
+ u8 res0028[4];
+ __be32 cnappsr;/* 0x002c Core Nap Previous Status Register */
+ u8 res0030[4];
+ __be32 cwaitsr;/* 0x0034 Core Wait Status Register */
+ u8 res0038[4];
+ __be32 cwdtdsr;/* 0x003c Core Watchdog Detect Status Register */
+ __be32 powmgtcsr; /* 0x0040 PM Control Register */
+#define RCPM_POWMGTCSR_SLP 0x0002
+ u8 res0044[12];
+ __be32 ippdexpcr; /* 0x0050 IP Powerdown Exception Control Register */
+ u8 res0054[16];
+ __be32 cpmimr; /* 0x0064 Core PM IRQ Mask Register */
+ u8 res0068[4];
+ __be32 cpmcimr;/* 0x006c Core PM Critical IRQ Mask Register */
+ u8 res0070[4];
+ __be32 cpmmcmr;/* 0x0074 Core PM Machine Check Mask Register */
+ u8 res0078[4];
+ __be32 cpmnmimr; /* 0x007c Core PM NMI Mask Register */
+ u8 res0080[4];
+ __be32 ctbenr; /* 0x0084 Core Time Base Enable Register */
+ u8
[PATCH v5] powerpc/rcpm: add RCPM driver
From: Tang Yuantian yuantian.t...@freescale.com
There is a RCPM (Run Control/Power Management) in Freescale QorIQ
series processors. The device performs tasks associated with device
run control and power management.
The driver implements some features: mask/unmask irq, enter/exit low
power states, freeze time base, etc.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v5:
- update chassis version for t1040 in bindings
v4:
- refine bindings document
v3:
- added static and __init modifier to fsl_rcpm_init
v2:
- fix code style issues
- refine compatible string match part
Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 44 +++
arch/powerpc/include/asm/fsl_guts.h| 105 +++
arch/powerpc/include/asm/fsl_pm.h | 48 +++
arch/powerpc/platforms/85xx/Kconfig| 1 +
arch/powerpc/sysdev/Kconfig| 5 +
arch/powerpc/sysdev/Makefile | 1 +
arch/powerpc/sysdev/fsl_rcpm.c | 338 +
7 files changed, 542 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/fsl/rcpm.txt
create mode 100644 arch/powerpc/include/asm/fsl_pm.h
create mode 100644 arch/powerpc/sysdev/fsl_rcpm.c
diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
new file mode 100644
index 000..dc52f70
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
@@ -0,0 +1,44 @@
+* Run Control and Power Management
+
+The RCPM performs all device-level tasks associated with device run control
+and power management.
+
+Required properites:
+ - reg : Offset and length of the register set of RCPM block.
+ - compatible : Sould contain a chip-specific RCPM block compatible string
+ and (if applicable) may contain a chassis-version RCPM compatible
string.
+ Chip-specific strings are of the form fsl,chip-rcpm, such as:
+ * fsl,p2041-rcpm
+ * fsl,p3041-rcpm
+ * fsl,p4080-rcpm
+ * fsl,p5020-rcpm
+ * fsl,p5040-rcpm
+ * fsl,t4240-rcpm
+ * fsl,b4420-rcpm
+ * fsl,b4860-rcpm
+
+ Chassis-version RCPM strings include:
+ * fsl,qoriq-rcpm-1.0: for chassis 1.0 rcpm
+ * fsl,qoriq-rcpm-2.0: for chassis 2.0 rcpm
+ * fsl,qoriq-rcpm-2.1: for chassis 2.1 rcpm
+
+All references to 1.0 and 2.0 refer to the QorIQ chassis version to
+which the chip complies.
+Chassis VersionExample Chips
+------
+1.0p4080, p5020, p5040, p2041, p3041
+2.0t4240, b4860, b4420
+2.1t1040
+
+Example:
+The RCPM node for T4240:
+ rcpm: global-utilities@e2000 {
+ compatible = fsl,t4240-rcpm, fsl,qoriq-rcpm-2.0;
+ reg = 0xe2000 0x1000;
+ };
+
+The RCPM node for P4080:
+ rcpm: global-utilities@e2000 {
+ compatible = fsl,qoriq-rcpm-1.0;
+ reg = 0xe2000 0x1000;
+ };
diff --git a/arch/powerpc/include/asm/fsl_guts.h
b/arch/powerpc/include/asm/fsl_guts.h
index 43b6bb1..a67413c 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -188,5 +188,110 @@ static inline void guts_set_pmuxcr_dma(struct ccsr_guts
__iomem *guts,
#endif
+struct ccsr_rcpm_v1 {
+ u8 res[4];
+ __be32 cdozsr; /* 0x0004 Core Doze Status Register */
+ u8 res0008[4];
+ __be32 cdozcr; /* 0x000c Core Doze Control Register */
+ u8 res0010[4];
+ __be32 cnapsr; /* 0x0014 Core Nap Status Register */
+ u8 res0018[4];
+ __be32 cnapcr; /* 0x001c Core Nap Control Register */
+ u8 res0020[4];
+ __be32 cdozpsr;/* 0x0024 Core Doze Previous Status Register */
+ u8 res0028[4];
+ __be32 cnappsr;/* 0x002c Core Nap Previous Status Register */
+ u8 res0030[4];
+ __be32 cwaitsr;/* 0x0034 Core Wait Status Register */
+ u8 res0038[4];
+ __be32 cwdtdsr;/* 0x003c Core Watchdog Detect Status Register */
+ __be32 powmgtcsr; /* 0x0040 PM ControlStatus Register */
+#define RCPM_POWMGTCSR_SLP 0x0002
+ u8 res0044[12];
+ __be32 ippdexpcr; /* 0x0050 IP Powerdown Exception Control Register */
+ u8 res0054[16];
+ __be32 cpmimr; /* 0x0064 Core PM IRQ Mask Register */
+ u8 res0068[4];
+ __be32 cpmcimr;/* 0x006c Core PM Critical IRQ Mask Register */
+ u8 res0070[4];
+ __be32 cpmmcmr;/* 0x0074 Core PM Machine Check Mask Register */
+ u8 res0078[4];
+ __be32 cpmnmimr; /* 0x007c Core PM NMI Mask Register */
+ u8 res0080[4];
+ __be32 ctbenr; /*
