[PATCH v6 00/17] powerpc/vas: Enable VAS
POWER9 introduces a hardware subsystem referred to as the Virtual Accelerator Switchboard (VAS). VAS allows kernel subsystems and user space processes to directly access the Nest Accelerator (NX) engines which implement compression and encryption algorithms in the hardware. NX has been in Power processors since Power7+, but access to the NX engines was through the 'icswx' instruction which is only available to the kernel/hypervisor. Starting with POWER9, access to the NX engines is provided to both kernel and user space processes through VAS. The switchboard (i.e VAS) multiplexes accesses between "receivers" and "senders", where the "receivers" are typically the NX engines and the "senders" are the kernel subsystems and user processors that wish to access the receivers (NX engines). Once a sender is "connected" to a receiver through the switchboard, the senders can submit compression/ encryption requests to the hardware using the new (PowerISA 3.0) "copy" and "paste" instructions. Senders can also send "empty" messages to the receiver. If the receiver is executing a WAIT instruction, this empty message serves to have the receiver resume from the next instruction. (i.e acts as "wake up" message). This usage of VAS is referred to as "Fast thread-wakeup". Provides: This patch set: - configures the VAS subsystems in the hardware - provides kernel interfaces to drivers like NX-842 and NX-FTW (new) to open receive and send/receive windows and to submit copy/paste (i.e compression) requests to the NX engines. - implements an NX-FTW driver for the fast thread-wake up mechanism. It provides the /dev/crypto/nx-ftw device node, and ioctls to allow users to use the FTW mechanism in VAS. Follow-on patch set(s) will allow user space processes to submit requests to the NX-GZIP engine (and possibly other engines). Requires: This patch set needs corresponding VAS/NX skiboot patches which were merged into skiboot tree. i.e skiboot must include: commit 3b3c596 (NX: Add P9 NX support for 842 compression engine) Testing: In-kernel compression requests were tested on DD1 POWER9 hardware using the following NX-842 patch set from Haren Myneni: https://lists.ozlabs.org/pipermail/linuxppc-dev/2017-July/160620.html The ability to setup user space send/receive windows for FTW was tested on DD1 hardware. The actual copy/paste of the empty messages is not yet supported in hardware and that functionality was tested on DD2 simics software. Git Tree: https://github.com/sukadev/linux/ Branch: vas-kern-v6 Thanks to input from Ben Herrenschmidt, Michael Neuling, Michael Ellerman, Robert Blackmore and Haren Myneni. Changelog[v6] - Add support for user space send/receive FTW windows - Add a new, NX-FTW driver which provides the FTW user interface Changelog[v5] - [Ben Herrenschmidt] Make VAS a platform device in the device tree and use the core platform functions to parse the VAS properties. Map the VAS MMIO regions as non-cachable and paste regions as cachable. Use CONFIG_PPC_VAS rather than CONFIG_VAS; Don't assume VAS ids are sequential. - Copy the FIFO address as is into LFIFO_BAR (don't shift it). Changelog[v4] Comments from Michael Neuling: - Move VAS code from drivers/misc/vas to arch/powerpc/platforms/powernv since VAS only provides interfaces to other drivers like NX-842. - Drop vas-internal.h and use vas.h in separate dirs for VAS internal, kernel API and user API - Rather than create 6 separate device tree properties windows and window context, combine them into 6 "reg" properties. - Drop vas_window_reset() since windows are reset/cleared before being assigned to kernel/users. - Use ilog2() and radix_enabled() helpers Changelog[v3] - Rebase to v4.11-rc1 - Add interfaces to initialize send/receive window attributes to defaults that drivers can use (see arch/powerpc/include/asm/vas.h) - Modify interface vas_paste() to return 0 or error code - Fix a bug in setting Translation Control Mode (0b11 not 0x11) - Enable send-window-credit checking - Reorg code in vas_win_close() - Minor reorgs and tweaks to register field settings to make it easier to add support for user space windows. - Skip writing to read-only registers - Start window indexing from 0 rather than 1 Changelog[v2] - Use vas-id, HVWC, UWC and paste address, entries from device tree rather than defining/computing them in kernel and reorg code. Sukadev Bhattiprolu (17): powerpc/vas: Define macros, register
[PATCH v6 00/17] powerpc/vas: Enable VAS
POWER9 introduces a hardware subsystem referred to as the Virtual Accelerator Switchboard (VAS). VAS allows kernel subsystems and user space processes to directly access the Nest Accelerator (NX) engines which implement compression and encryption algorithms in the hardware. NX has been in Power processors since Power7+, but access to the NX engines was through the 'icswx' instruction which is only available to the kernel/hypervisor. Starting with POWER9, access to the NX engines is provided to both kernel and user space processes through VAS. The switchboard (i.e VAS) multiplexes accesses between "receivers" and "senders", where the "receivers" are typically the NX engines and the "senders" are the kernel subsystems and user processors that wish to access the receivers (NX engines). Once a sender is "connected" to a receiver through the switchboard, the senders can submit compression/ encryption requests to the hardware using the new (PowerISA 3.0) "copy" and "paste" instructions. Senders can also send "empty" messages to the receiver. If the receiver is executing a WAIT instruction, this empty message serves to have the receiver resume from the next instruction. (i.e acts as "wake up" message). This usage of VAS is referred to as "Fast thread-wakeup". Provides: This patch set: - configures the VAS subsystems in the hardware - provides kernel interfaces to drivers like NX-842 and NX-FTW (new) to open receive and send/receive windows and to submit copy/paste (i.e compression) requests to the NX engines. - implements an NX-FTW driver for the fast thread-wake up mechanism. It provides the /dev/crypto/nx-ftw device node, and ioctls to allow users to use the FTW mechanism in VAS. Follow-on patch set(s) will allow user space processes to submit requests to the NX-GZIP engine (and possibly other engines). Requires: This patch set needs corresponding VAS/NX skiboot patches which were merged into skiboot tree. i.e skiboot must include: commit 3b3c596 (NX: Add P9 NX support for 842 compression engine) Testing: In-kernel compression requests were tested on DD1 POWER9 hardware using the following NX-842 patch set from Haren Myneni: https://lists.ozlabs.org/pipermail/linuxppc-dev/2017-July/160620.html The ability to setup user space send/receive windows for FTW was tested on DD1 hardware. The actual copy/paste of the empty messages is not yet supported in hardware and that functionality was tested on DD2 simics software. Git Tree: https://github.com/sukadev/linux/ Branch: vas-kern-v6 Thanks to input from Ben Herrenschmidt, Michael Neuling, Michael Ellerman, Robert Blackmore and Haren Myneni. Changelog[v6] - Add support for user space send/receive FTW windows - Add a new, NX-FTW driver which provides the FTW user interface Changelog[v5] - [Ben Herrenschmidt] Make VAS a platform device in the device tree and use the core platform functions to parse the VAS properties. Map the VAS MMIO regions as non-cachable and paste regions as cachable. Use CONFIG_PPC_VAS rather than CONFIG_VAS; Don't assume VAS ids are sequential. - Copy the FIFO address as is into LFIFO_BAR (don't shift it). Changelog[v4] Comments from Michael Neuling: - Move VAS code from drivers/misc/vas to arch/powerpc/platforms/powernv since VAS only provides interfaces to other drivers like NX-842. - Drop vas-internal.h and use vas.h in separate dirs for VAS internal, kernel API and user API - Rather than create 6 separate device tree properties windows and window context, combine them into 6 "reg" properties. - Drop vas_window_reset() since windows are reset/cleared before being assigned to kernel/users. - Use ilog2() and radix_enabled() helpers Changelog[v3] - Rebase to v4.11-rc1 - Add interfaces to initialize send/receive window attributes to defaults that drivers can use (see arch/powerpc/include/asm/vas.h) - Modify interface vas_paste() to return 0 or error code - Fix a bug in setting Translation Control Mode (0b11 not 0x11) - Enable send-window-credit checking - Reorg code in vas_win_close() - Minor reorgs and tweaks to register field settings to make it easier to add support for user space windows. - Skip writing to read-only registers - Start window indexing from 0 rather than 1 Changelog[v2] - Use vas-id, HVWC, UWC and paste address, entries from device tree rather than defining/computing them in kernel and reorg code. Sukadev Bhattiprolu (17): powerpc/vas: Define macros, register
