On Tue, Apr 29, 2014 at 11:34:00AM +0100, Lorenzo Pieralisi wrote:
> Sorry for the delay in replying. Those cache bindings need an ACK
> to get merged, and were introduced so that idle states can retrieve
> power domain information for caches. I am going to revive the idle
> bindings thread to see
On Tue, Apr 08, 2014 at 04:39:25PM +0100, Borislav Petkov wrote:
> On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
> > The Krait L1/L2 error reporting hardware is made up a per-CPU
> > interrupt for the L1 cache and a SPI interrupt for the L2.
> >
> > Cc: Lorenzo Pieralisi
> > Cc:
On Tue, Apr 08, 2014 at 04:39:25PM +0100, Borislav Petkov wrote:
On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
The Krait L1/L2 error reporting hardware is made up a per-CPU
interrupt for the L1 cache and a SPI interrupt for the L2.
Cc: Lorenzo Pieralisi
On Tue, Apr 29, 2014 at 11:34:00AM +0100, Lorenzo Pieralisi wrote:
Sorry for the delay in replying. Those cache bindings need an ACK
to get merged, and were introduced so that idle states can retrieve
power domain information for caches. I am going to revive the idle
bindings thread to see
On 04/08/14 08:39, Borislav Petkov wrote:
> On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
>> The Krait L1/L2 error reporting hardware is made up a per-CPU
>> interrupt for the L1 cache and a SPI interrupt for the L2.
>>
>> Cc: Lorenzo Pieralisi
>> Cc: Mark Rutland
>> Cc: Kumar
On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
> The Krait L1/L2 error reporting hardware is made up a per-CPU
> interrupt for the L1 cache and a SPI interrupt for the L2.
>
> Cc: Lorenzo Pieralisi
> Cc: Mark Rutland
> Cc: Kumar Gala
> Cc:
> Signed-off-by: Stephen Boyd
> ---
>
On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
The Krait L1/L2 error reporting hardware is made up a per-CPU
interrupt for the L1 cache and a SPI interrupt for the L2.
Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala
On 04/08/14 08:39, Borislav Petkov wrote:
On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
The Krait L1/L2 error reporting hardware is made up a per-CPU
interrupt for the L1 cache and a SPI interrupt for the L2.
Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Cc: Mark Rutland
The Krait L1/L2 error reporting hardware is made up a per-CPU
interrupt for the L1 cache and a SPI interrupt for the L2.
Cc: Lorenzo Pieralisi
Cc: Mark Rutland
Cc: Kumar Gala
Cc:
Signed-off-by: Stephen Boyd
---
Documentation/devicetree/bindings/arm/cache.txt | 48 -
The Krait L1/L2 error reporting hardware is made up a per-CPU
interrupt for the L1 cache and a SPI interrupt for the L2.
Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Cc: devicet...@vger.kernel.org
Signed-off-by: Stephen
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