Re: [PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts

2014-04-29 Thread Borislav Petkov
On Tue, Apr 29, 2014 at 11:34:00AM +0100, Lorenzo Pieralisi wrote:
> Sorry for the delay in replying. Those cache bindings need an ACK
> to get merged, and were introduced so that idle states can retrieve
> power domain information for caches. I am going to revive the idle
> bindings thread to see what we can/should merge of these bindings as
> things stand, I really hope this won't block the series any further,
> otherwise we can rework the patches so that this series can get in
> first, or simplify my series to allow both to get merged as soon as
> possible without compromising future requirements.

Right, I think this is Stephen's call. AFAIR, the current state of
affairs is for a followup patchset to come up which I can ack for the
EDAC bits and then another maintainer picks the whole thing up.

-- 
Regards/Gruss,
Boris.

Sent from a fat crate under my desk. Formatting is fine.
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Re: [PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts

2014-04-29 Thread Lorenzo Pieralisi
On Tue, Apr 08, 2014 at 04:39:25PM +0100, Borislav Petkov wrote:
> On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
> > The Krait L1/L2 error reporting hardware is made up a per-CPU
> > interrupt for the L1 cache and a SPI interrupt for the L2.
> > 
> > Cc: Lorenzo Pieralisi 
> > Cc: Mark Rutland 
> > Cc: Kumar Gala 
> > Cc: 
> > Signed-off-by: Stephen Boyd 
> > ---
> >  Documentation/devicetree/bindings/arm/cache.txt | 48 
> > -
> >  1 file changed, 47 insertions(+), 1 deletion(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/cache.txt 
> > b/Documentation/devicetree/bindings/arm/cache.txt
> > index b90fcc7c53cf..d7357e777399 100644
> > --- a/Documentation/devicetree/bindings/arm/cache.txt
> > +++ b/Documentation/devicetree/bindings/arm/cache.txt
> 
> Right, that's http://www.spinics.net/lists/arm-kernel/msg308540.html
> 
> So whoever picks those patches up, Lorenzo's doc needs to be in his tree
> first too.

Sorry for the delay in replying. Those cache bindings need an ACK to get
merged, and were introduced so that idle states can retrieve power domain
information for caches. I am going to revive the idle bindings thread
to see what we can/should merge of these bindings as things stand, I
really hope this won't block the series any further, otherwise we can
rework the patches so that this series can get in first, or simplify my
series to allow both to get merged as soon as possible without compromising
future requirements.

Thanks,
Lorenzo

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Re: [PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts

2014-04-29 Thread Lorenzo Pieralisi
On Tue, Apr 08, 2014 at 04:39:25PM +0100, Borislav Petkov wrote:
 On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
  The Krait L1/L2 error reporting hardware is made up a per-CPU
  interrupt for the L1 cache and a SPI interrupt for the L2.
  
  Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
  Cc: Mark Rutland mark.rutl...@arm.com
  Cc: Kumar Gala ga...@codeaurora.org
  Cc: devicet...@vger.kernel.org
  Signed-off-by: Stephen Boyd sb...@codeaurora.org
  ---
   Documentation/devicetree/bindings/arm/cache.txt | 48 
  -
   1 file changed, 47 insertions(+), 1 deletion(-)
  
  diff --git a/Documentation/devicetree/bindings/arm/cache.txt 
  b/Documentation/devicetree/bindings/arm/cache.txt
  index b90fcc7c53cf..d7357e777399 100644
  --- a/Documentation/devicetree/bindings/arm/cache.txt
  +++ b/Documentation/devicetree/bindings/arm/cache.txt
 
 Right, that's http://www.spinics.net/lists/arm-kernel/msg308540.html
 
 So whoever picks those patches up, Lorenzo's doc needs to be in his tree
 first too.

Sorry for the delay in replying. Those cache bindings need an ACK to get
merged, and were introduced so that idle states can retrieve power domain
information for caches. I am going to revive the idle bindings thread
to see what we can/should merge of these bindings as things stand, I
really hope this won't block the series any further, otherwise we can
rework the patches so that this series can get in first, or simplify my
series to allow both to get merged as soon as possible without compromising
future requirements.

Thanks,
Lorenzo

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Re: [PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts

2014-04-29 Thread Borislav Petkov
On Tue, Apr 29, 2014 at 11:34:00AM +0100, Lorenzo Pieralisi wrote:
 Sorry for the delay in replying. Those cache bindings need an ACK
 to get merged, and were introduced so that idle states can retrieve
 power domain information for caches. I am going to revive the idle
 bindings thread to see what we can/should merge of these bindings as
 things stand, I really hope this won't block the series any further,
 otherwise we can rework the patches so that this series can get in
 first, or simplify my series to allow both to get merged as soon as
 possible without compromising future requirements.

Right, I think this is Stephen's call. AFAIR, the current state of
affairs is for a followup patchset to come up which I can ack for the
EDAC bits and then another maintainer picks the whole thing up.

-- 
Regards/Gruss,
Boris.

Sent from a fat crate under my desk. Formatting is fine.
--
--
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Re: [PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts

2014-04-08 Thread Stephen Boyd
On 04/08/14 08:39, Borislav Petkov wrote:
> On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
>> The Krait L1/L2 error reporting hardware is made up a per-CPU
>> interrupt for the L1 cache and a SPI interrupt for the L2.
>>
>> Cc: Lorenzo Pieralisi 
>> Cc: Mark Rutland 
>> Cc: Kumar Gala 
>> Cc: 
>> Signed-off-by: Stephen Boyd 
>> ---
>>  Documentation/devicetree/bindings/arm/cache.txt | 48 
>> -
>>  1 file changed, 47 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/cache.txt 
>> b/Documentation/devicetree/bindings/arm/cache.txt
>> index b90fcc7c53cf..d7357e777399 100644
>> --- a/Documentation/devicetree/bindings/arm/cache.txt
>> +++ b/Documentation/devicetree/bindings/arm/cache.txt
> Right, that's http://www.spinics.net/lists/arm-kernel/msg308540.html
>
> So whoever picks those patches up, Lorenzo's doc needs to be in his tree
> first too.
>
> How about I review the EDAC part and an arm maintainer picks the whole
> series up? Would that be easier, logistically?
>

That sounds fine if you want to give an ack on the edac changes. I can
route it through arm-soc.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation

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Re: [PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts

2014-04-08 Thread Borislav Petkov
On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
> The Krait L1/L2 error reporting hardware is made up a per-CPU
> interrupt for the L1 cache and a SPI interrupt for the L2.
> 
> Cc: Lorenzo Pieralisi 
> Cc: Mark Rutland 
> Cc: Kumar Gala 
> Cc: 
> Signed-off-by: Stephen Boyd 
> ---
>  Documentation/devicetree/bindings/arm/cache.txt | 48 
> -
>  1 file changed, 47 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cache.txt 
> b/Documentation/devicetree/bindings/arm/cache.txt
> index b90fcc7c53cf..d7357e777399 100644
> --- a/Documentation/devicetree/bindings/arm/cache.txt
> +++ b/Documentation/devicetree/bindings/arm/cache.txt

Right, that's http://www.spinics.net/lists/arm-kernel/msg308540.html

So whoever picks those patches up, Lorenzo's doc needs to be in his tree
first too.

How about I review the EDAC part and an arm maintainer picks the whole
series up? Would that be easier, logistically?

-- 
Regards/Gruss,
Boris.

Sent from a fat crate under my desk. Formatting is fine.
--
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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Re: [PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts

2014-04-08 Thread Borislav Petkov
On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
 The Krait L1/L2 error reporting hardware is made up a per-CPU
 interrupt for the L1 cache and a SPI interrupt for the L2.
 
 Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
 Cc: Mark Rutland mark.rutl...@arm.com
 Cc: Kumar Gala ga...@codeaurora.org
 Cc: devicet...@vger.kernel.org
 Signed-off-by: Stephen Boyd sb...@codeaurora.org
 ---
  Documentation/devicetree/bindings/arm/cache.txt | 48 
 -
  1 file changed, 47 insertions(+), 1 deletion(-)
 
 diff --git a/Documentation/devicetree/bindings/arm/cache.txt 
 b/Documentation/devicetree/bindings/arm/cache.txt
 index b90fcc7c53cf..d7357e777399 100644
 --- a/Documentation/devicetree/bindings/arm/cache.txt
 +++ b/Documentation/devicetree/bindings/arm/cache.txt

Right, that's http://www.spinics.net/lists/arm-kernel/msg308540.html

So whoever picks those patches up, Lorenzo's doc needs to be in his tree
first too.

How about I review the EDAC part and an arm maintainer picks the whole
series up? Would that be easier, logistically?

-- 
Regards/Gruss,
Boris.

Sent from a fat crate under my desk. Formatting is fine.
--
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
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Re: [PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts

2014-04-08 Thread Stephen Boyd
On 04/08/14 08:39, Borislav Petkov wrote:
 On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
 The Krait L1/L2 error reporting hardware is made up a per-CPU
 interrupt for the L1 cache and a SPI interrupt for the L2.

 Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
 Cc: Mark Rutland mark.rutl...@arm.com
 Cc: Kumar Gala ga...@codeaurora.org
 Cc: devicet...@vger.kernel.org
 Signed-off-by: Stephen Boyd sb...@codeaurora.org
 ---
  Documentation/devicetree/bindings/arm/cache.txt | 48 
 -
  1 file changed, 47 insertions(+), 1 deletion(-)

 diff --git a/Documentation/devicetree/bindings/arm/cache.txt 
 b/Documentation/devicetree/bindings/arm/cache.txt
 index b90fcc7c53cf..d7357e777399 100644
 --- a/Documentation/devicetree/bindings/arm/cache.txt
 +++ b/Documentation/devicetree/bindings/arm/cache.txt
 Right, that's http://www.spinics.net/lists/arm-kernel/msg308540.html

 So whoever picks those patches up, Lorenzo's doc needs to be in his tree
 first too.

 How about I review the EDAC part and an arm maintainer picks the whole
 series up? Would that be easier, logistically?


That sounds fine if you want to give an ack on the edac changes. I can
route it through arm-soc.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation

--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
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[PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts

2014-04-04 Thread Stephen Boyd
The Krait L1/L2 error reporting hardware is made up a per-CPU
interrupt for the L1 cache and a SPI interrupt for the L2.

Cc: Lorenzo Pieralisi 
Cc: Mark Rutland 
Cc: Kumar Gala 
Cc: 
Signed-off-by: Stephen Boyd 
---
 Documentation/devicetree/bindings/arm/cache.txt | 48 -
 1 file changed, 47 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/cache.txt 
b/Documentation/devicetree/bindings/arm/cache.txt
index b90fcc7c53cf..d7357e777399 100644
--- a/Documentation/devicetree/bindings/arm/cache.txt
+++ b/Documentation/devicetree/bindings/arm/cache.txt
@@ -37,7 +37,9 @@ This document provides the device tree bindings for ARM 
architected caches.
- compatible
Usage: Required
Value type: 
-   Definition: value shall be "arm,arch-cache".
+   Definition: shall be one of:
+   "arm,arch-cache"
+   "qcom,arch-cache"
 
- power-domain
Usage: Optional
@@ -45,6 +47,12 @@ This document provides the device tree bindings for ARM 
architected caches.
Definition: A phandle and power domain specifier as defined by
bindings of power domain specified by [3].
 
+   - interrupts
+   Usage: Optional for caches with compatible of "qcom,arch-cache"
+   Value type: 
+   Definition: Error interrupt associated with this cache.
+
+
 Example(dual-cluster big.LITTLE system 32-bit)
 
cpus {
@@ -156,6 +164,44 @@ Example(dual-cluster big.LITTLE system 32-bit)
};
};
 
+Example (Krait 32-bit system):
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "qcom,krait";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <_0>;
+
+   L1_0: l1-cache {
+   compatible = "qcom,arch-cache";
+   interrupts = <1 14 0x104>;
+   next-level-cache = <>;
+   };
+
+   L2: l2-cache {
+   compatible = "qcom,arch-cache";
+   interrupts = <0 2 0x4>;
+   };
+   };
+
+   cpu@1 {
+   compatible = "qcom,krait";
+   device_type = "cpu";
+   reg = <1>;
+   next-level-cache = <_1>;
+
+   L1_1: l1-cache {
+   compatible = "qcom,arch-cache";
+   interrupts = <1 14 0x204>;
+   next-level-cache = <>;
+   };
+   };
+   };
+
 [1] ARM Architecture Reference Manuals
 http://infocenter.arm.com/help/index.jsp
 
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[PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts

2014-04-04 Thread Stephen Boyd
The Krait L1/L2 error reporting hardware is made up a per-CPU
interrupt for the L1 cache and a SPI interrupt for the L2.

Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Cc: devicet...@vger.kernel.org
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
 Documentation/devicetree/bindings/arm/cache.txt | 48 -
 1 file changed, 47 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/cache.txt 
b/Documentation/devicetree/bindings/arm/cache.txt
index b90fcc7c53cf..d7357e777399 100644
--- a/Documentation/devicetree/bindings/arm/cache.txt
+++ b/Documentation/devicetree/bindings/arm/cache.txt
@@ -37,7 +37,9 @@ This document provides the device tree bindings for ARM 
architected caches.
- compatible
Usage: Required
Value type: string
-   Definition: value shall be arm,arch-cache.
+   Definition: shall be one of:
+   arm,arch-cache
+   qcom,arch-cache
 
- power-domain
Usage: Optional
@@ -45,6 +47,12 @@ This document provides the device tree bindings for ARM 
architected caches.
Definition: A phandle and power domain specifier as defined by
bindings of power domain specified by [3].
 
+   - interrupts
+   Usage: Optional for caches with compatible of qcom,arch-cache
+   Value type: prop-encoded-array
+   Definition: Error interrupt associated with this cache.
+
+
 Example(dual-cluster big.LITTLE system 32-bit)
 
cpus {
@@ -156,6 +164,44 @@ Example(dual-cluster big.LITTLE system 32-bit)
};
};
 
+Example (Krait 32-bit system):
+
+   cpus {
+   #address-cells = 1;
+   #size-cells = 0;
+
+   cpu@0 {
+   compatible = qcom,krait;
+   device_type = cpu;
+   reg = 0;
+   next-level-cache = L1_0;
+
+   L1_0: l1-cache {
+   compatible = qcom,arch-cache;
+   interrupts = 1 14 0x104;
+   next-level-cache = L2;
+   };
+
+   L2: l2-cache {
+   compatible = qcom,arch-cache;
+   interrupts = 0 2 0x4;
+   };
+   };
+
+   cpu@1 {
+   compatible = qcom,krait;
+   device_type = cpu;
+   reg = 1;
+   next-level-cache = L1_1;
+
+   L1_1: l1-cache {
+   compatible = qcom,arch-cache;
+   interrupts = 1 14 0x204;
+   next-level-cache = L2;
+   };
+   };
+   };
+
 [1] ARM Architecture Reference Manuals
 http://infocenter.arm.com/help/index.jsp
 
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hosted by The Linux Foundation

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