Hi,
I have some documentation edits for you to consider:
On 12/5/18 2:59 AM, Kulkarni, Ganapatrao wrote:
> The SoC has PMU support in its L3 cache controller (L3C) and in the
> DDR4 Memory Controller (DMC).
>
> Signed-off-by: Ganapatrao Kulkarni
> ---
> Documentation/perf/thunderx2-pmu.txt |
Hi,
I have some documentation edits for you to consider:
On 12/5/18 2:59 AM, Kulkarni, Ganapatrao wrote:
> The SoC has PMU support in its L3 cache controller (L3C) and in the
> DDR4 Memory Controller (DMC).
>
> Signed-off-by: Ganapatrao Kulkarni
> ---
> Documentation/perf/thunderx2-pmu.txt |
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