Re: [PATCHv2 04/10] fbdev: ssd1307fb: Unify init code and obtain hw specific bits from DT
On Sun, Mar 01, 2015 at 11:27:57PM +0100, Thomas Niederprüm wrote: > The SSD130X controllers are very similar from the configuration point of view. > The configuration registers for the SSD1305/6/7 are bit identical (except the > the VHCOM register and the the default values for clock setup register). This > patch unifies the init code of the controller and adds hardware specific > properties to DT that are needed to correctly initialize the device. > > The SSD130X can be wired to the OLED panel in various ways. Even for the > same controller this wiring can differ from one display module to another > and can not be probed by software. The added DT properties reflect these > hardware decisions of the display module manufacturer. > The 'com-sequential', 'com-lrremap' and 'com-invdir' values define different > possibilities for the COM signals pin configuration and readout direction > of the video memory. The 'segment-remap' allows the inversion of the memory- > to-pin mapping ultimately inverting the order of the controllers output pins. > The 'prechargepX' values need to be adapted according the capacitance of the > OLEDs pixel cells. > > So far these hardware specific bits are hard coded in the init code, making > the driver usable only for one certain wiring of the controller. This patch > makes the driver usable with all possible hardware setups, given a valid hw > description in DT. If the values are not set in DT the default values > according to the controllers datasheet are assumed. Unfortunately, this is not a reasonable thing to do, even if you fix the existing user, there's still the case where you have an older DT with a newer kernel. Keeping (and documenting) the previous defaults is the only easy way to support this. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
Re: [PATCHv2 04/10] fbdev: ssd1307fb: Unify init code and obtain hw specific bits from DT
On Sun, Mar 01, 2015 at 11:27:57PM +0100, Thomas Niederprüm wrote: The SSD130X controllers are very similar from the configuration point of view. The configuration registers for the SSD1305/6/7 are bit identical (except the the VHCOM register and the the default values for clock setup register). This patch unifies the init code of the controller and adds hardware specific properties to DT that are needed to correctly initialize the device. The SSD130X can be wired to the OLED panel in various ways. Even for the same controller this wiring can differ from one display module to another and can not be probed by software. The added DT properties reflect these hardware decisions of the display module manufacturer. The 'com-sequential', 'com-lrremap' and 'com-invdir' values define different possibilities for the COM signals pin configuration and readout direction of the video memory. The 'segment-remap' allows the inversion of the memory- to-pin mapping ultimately inverting the order of the controllers output pins. The 'prechargepX' values need to be adapted according the capacitance of the OLEDs pixel cells. So far these hardware specific bits are hard coded in the init code, making the driver usable only for one certain wiring of the controller. This patch makes the driver usable with all possible hardware setups, given a valid hw description in DT. If the values are not set in DT the default values according to the controllers datasheet are assumed. Unfortunately, this is not a reasonable thing to do, even if you fix the existing user, there's still the case where you have an older DT with a newer kernel. Keeping (and documenting) the previous defaults is the only easy way to support this. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
[PATCHv2 04/10] fbdev: ssd1307fb: Unify init code and obtain hw specific bits from DT
The SSD130X controllers are very similar from the configuration point of view.
The configuration registers for the SSD1305/6/7 are bit identical (except the
the VHCOM register and the the default values for clock setup register). This
patch unifies the init code of the controller and adds hardware specific
properties to DT that are needed to correctly initialize the device.
The SSD130X can be wired to the OLED panel in various ways. Even for the
same controller this wiring can differ from one display module to another
and can not be probed by software. The added DT properties reflect these
hardware decisions of the display module manufacturer.
The 'com-sequential', 'com-lrremap' and 'com-invdir' values define different
possibilities for the COM signals pin configuration and readout direction
of the video memory. The 'segment-remap' allows the inversion of the memory-
to-pin mapping ultimately inverting the order of the controllers output pins.
The 'prechargepX' values need to be adapted according the capacitance of the
OLEDs pixel cells.
So far these hardware specific bits are hard coded in the init code, making
the driver usable only for one certain wiring of the controller. This patch
makes the driver usable with all possible hardware setups, given a valid hw
description in DT. If the values are not set in DT the default values
according to the controllers datasheet are assumed. This implies that this
patch changes the existing behaviour with respect to the segment remap for
the SSD1307 when the corresponding property is not present in DT. The example
in the DT bindings documentation is updated to reflect this change.
Note that the SSD1306 does not seem to be using the configuration written to
the registers at all. Nevertheless an example is added to the DT bindings
documentation that would lead to the same configuration as the current init
code.
Signed-off-by: Thomas Niederprüm
---
.../devicetree/bindings/video/ssd1307fb.txt| 22 +++
drivers/video/fbdev/ssd1307fb.c| 195 -
2 files changed, 138 insertions(+), 79 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/ssd1307fb.txt
b/Documentation/devicetree/bindings/video/ssd1307fb.txt
index 7a12542..6bdd69b 100644
--- a/Documentation/devicetree/bindings/video/ssd1307fb.txt
+++ b/Documentation/devicetree/bindings/video/ssd1307fb.txt
@@ -15,6 +15,15 @@ Required properties:
Optional properties:
- reset-active-low: Is the reset gpio is active on physical low?
+ - solomon,segment-remap: Display needs inverted data column to segment
mapping
+ - solomon,com-sequential: Display uses sequential COM pin configuration
+ - solomon,com-lrremap: Display uses left-right COM pin remap
+ - solomon,com-invdir: Display uses inverted COM pin scan direction
+ - solomon,com-offset: Offset of the first COM pin wired to the panel
+ - solomon,prechargep1: Length of deselect period (phase 1) in clock cycles.
+ - solomon,prechargep2: Length of precharge period (phase 2) in clock cycles.
+ This needs to be the higher, the higher the
capacitance
+ of the OLED's pixels is
[0]: Documentation/devicetree/bindings/pwm/pwm.txt
@@ -25,4 +34,17 @@ ssd1307: oled@3c {
pwms = < 4 3000>;
reset-gpios = < 7>;
reset-active-low;
+solomon,segment-remap;
+};
+
+ssd1306: oled@3c {
+compatible = "solomon,ssd1306fb-i2c";
+reg = <0x3c>;
+pwms = < 4 3000>;
+reset-gpios = < 7>;
+reset-active-low;
+solomon,segment-remap;
+solomon,com-lrremap;
+solomon,com-invdir;
+solomon,com-offset = <32>;
};
diff --git a/drivers/video/fbdev/ssd1307fb.c b/drivers/video/fbdev/ssd1307fb.c
index 25dd08d..b4880c0 100644
--- a/drivers/video/fbdev/ssd1307fb.c
+++ b/drivers/video/fbdev/ssd1307fb.c
@@ -17,6 +17,9 @@
#include
#include
+#define DEVID_SSD1306 6
+#define DEVID_SSD1307 7
+
#define SSD1307FB_DATA 0x40
#define SSD1307FB_COMMAND 0x80
@@ -39,22 +42,38 @@
#defineSSD1307FB_SET_COM_PINS_CONFIG 0xda
#defineSSD1307FB_SET_VCOMH 0xdb
+static u_int contrast = 128;
+module_param(contrast, uint, S_IRUGO);
+
struct ssd1307fb_par;
-struct ssd1307fb_ops {
- int (*init)(struct ssd1307fb_par *);
- int (*remove)(struct ssd1307fb_par *);
+struct ssd1307fb_deviceinfo {
+ int device_id;
+ u32 default_vcomh;
+ u32 default_dclk_div;
+ u32 default_dclk_frq;
};
struct ssd1307fb_par {
+ u32 com_invdir;
+ u32 com_lrremap;
+ u32 com_offset;
+ u32 com_seq;
+ u32 contrast;
+ u32 dclk_div;
+ u32 dclk_frq;
+ struct ssd1307fb_deviceinfo *device_info;
struct i2c_client *client;
u32 height;
struct fb_info *info;
- struct ssd1307fb_ops *ops;
u32 page_offset;
+ u32 prechargep1;
+ u32 prechargep2;
[PATCHv2 04/10] fbdev: ssd1307fb: Unify init code and obtain hw specific bits from DT
The SSD130X controllers are very similar from the configuration point of view.
The configuration registers for the SSD1305/6/7 are bit identical (except the
the VHCOM register and the the default values for clock setup register). This
patch unifies the init code of the controller and adds hardware specific
properties to DT that are needed to correctly initialize the device.
The SSD130X can be wired to the OLED panel in various ways. Even for the
same controller this wiring can differ from one display module to another
and can not be probed by software. The added DT properties reflect these
hardware decisions of the display module manufacturer.
The 'com-sequential', 'com-lrremap' and 'com-invdir' values define different
possibilities for the COM signals pin configuration and readout direction
of the video memory. The 'segment-remap' allows the inversion of the memory-
to-pin mapping ultimately inverting the order of the controllers output pins.
The 'prechargepX' values need to be adapted according the capacitance of the
OLEDs pixel cells.
So far these hardware specific bits are hard coded in the init code, making
the driver usable only for one certain wiring of the controller. This patch
makes the driver usable with all possible hardware setups, given a valid hw
description in DT. If the values are not set in DT the default values
according to the controllers datasheet are assumed. This implies that this
patch changes the existing behaviour with respect to the segment remap for
the SSD1307 when the corresponding property is not present in DT. The example
in the DT bindings documentation is updated to reflect this change.
Note that the SSD1306 does not seem to be using the configuration written to
the registers at all. Nevertheless an example is added to the DT bindings
documentation that would lead to the same configuration as the current init
code.
Signed-off-by: Thomas Niederprüm nied...@physik.uni-kl.de
---
.../devicetree/bindings/video/ssd1307fb.txt| 22 +++
drivers/video/fbdev/ssd1307fb.c| 195 -
2 files changed, 138 insertions(+), 79 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/ssd1307fb.txt
b/Documentation/devicetree/bindings/video/ssd1307fb.txt
index 7a12542..6bdd69b 100644
--- a/Documentation/devicetree/bindings/video/ssd1307fb.txt
+++ b/Documentation/devicetree/bindings/video/ssd1307fb.txt
@@ -15,6 +15,15 @@ Required properties:
Optional properties:
- reset-active-low: Is the reset gpio is active on physical low?
+ - solomon,segment-remap: Display needs inverted data column to segment
mapping
+ - solomon,com-sequential: Display uses sequential COM pin configuration
+ - solomon,com-lrremap: Display uses left-right COM pin remap
+ - solomon,com-invdir: Display uses inverted COM pin scan direction
+ - solomon,com-offset: Offset of the first COM pin wired to the panel
+ - solomon,prechargep1: Length of deselect period (phase 1) in clock cycles.
+ - solomon,prechargep2: Length of precharge period (phase 2) in clock cycles.
+ This needs to be the higher, the higher the
capacitance
+ of the OLED's pixels is
[0]: Documentation/devicetree/bindings/pwm/pwm.txt
@@ -25,4 +34,17 @@ ssd1307: oled@3c {
pwms = pwm 4 3000;
reset-gpios = gpio2 7;
reset-active-low;
+solomon,segment-remap;
+};
+
+ssd1306: oled@3c {
+compatible = solomon,ssd1306fb-i2c;
+reg = 0x3c;
+pwms = pwm 4 3000;
+reset-gpios = gpio2 7;
+reset-active-low;
+solomon,segment-remap;
+solomon,com-lrremap;
+solomon,com-invdir;
+solomon,com-offset = 32;
};
diff --git a/drivers/video/fbdev/ssd1307fb.c b/drivers/video/fbdev/ssd1307fb.c
index 25dd08d..b4880c0 100644
--- a/drivers/video/fbdev/ssd1307fb.c
+++ b/drivers/video/fbdev/ssd1307fb.c
@@ -17,6 +17,9 @@
#include linux/pwm.h
#include linux/delay.h
+#define DEVID_SSD1306 6
+#define DEVID_SSD1307 7
+
#define SSD1307FB_DATA 0x40
#define SSD1307FB_COMMAND 0x80
@@ -39,22 +42,38 @@
#defineSSD1307FB_SET_COM_PINS_CONFIG 0xda
#defineSSD1307FB_SET_VCOMH 0xdb
+static u_int contrast = 128;
+module_param(contrast, uint, S_IRUGO);
+
struct ssd1307fb_par;
-struct ssd1307fb_ops {
- int (*init)(struct ssd1307fb_par *);
- int (*remove)(struct ssd1307fb_par *);
+struct ssd1307fb_deviceinfo {
+ int device_id;
+ u32 default_vcomh;
+ u32 default_dclk_div;
+ u32 default_dclk_frq;
};
struct ssd1307fb_par {
+ u32 com_invdir;
+ u32 com_lrremap;
+ u32 com_offset;
+ u32 com_seq;
+ u32 contrast;
+ u32 dclk_div;
+ u32 dclk_frq;
+ struct ssd1307fb_deviceinfo *device_info;
struct i2c_client *client;
u32 height;
struct fb_info *info;
- struct ssd1307fb_ops *ops;
u32 page_offset;
+
