[PATCHv5 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC

2017-01-26 Thread Chris Packham 
From: Kalyan Kinthada 

This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs
from Marvell.

Signed-off-by: Kalyan Kinthada 
Signed-off-by: Chris Packham 
Acked-by: Rob Herring 
Acked-by: Sebastian Hesselbarth 
---

Notes:
Changes in v2:
- include sdio support for the 98DX4251
Changes in v3:
- None
Changes in v4:
- Correct some discrepencies between binding and driver.
- Collect acks from Rob and Sebastian
Changes in v5:
- Update bindings to reflect "gpo" pins
- Use mvebu_mmio_mpp_ctrl instead of armada_xp_mpp_ctrl (note this is 
reliant
  on changes queued in linux-pinctrl)

 .../pinctrl/marvell,armada-98dx3236-pinctrl.txt|  46 ++
 drivers/pinctrl/mvebu/pinctrl-armada-xp.c  | 156 +
 2 files changed, 202 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt

diff --git 
a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
new file mode 100644
index ..97aef67ee769
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
@@ -0,0 +1,46 @@
+* Marvell 98dx3236 pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage
+
+Required properties:
+- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
+- reg: register specifier of MPP registers
+
+This driver supports all 98dx3236, 98dx3336 and 98dx4251 variants
+
+name  pins functions
+
+mpp0  0gpo, spi0(mosi), dev(ad8)
+mpp1  1gpio, spi0(miso), dev(ad9)
+mpp2  2gpo, spi0(sck), dev(ad10)
+mpp3  3gpio, spi0(cs0), dev(ad11)
+mpp4  4gpio, spi0(cs1), smi(mdc), dev(cs0)
+mpp5  5gpio, pex(rsto), sd0(cmd), dev(bootcs)
+mpp6  6gpo, sd0(clk), dev(a2)
+mpp7  7gpio, sd0(d0), dev(ale0)
+mpp8  8gpio, sd0(d1), dev(ale1)
+mpp9  9gpio, sd0(d2), dev(ready0)
+mpp10 10   gpio, sd0(d3), dev(ad12)
+mpp11 11   gpio, uart1(rxd), uart0(cts), dev(ad13)
+mpp12 12   gpo, uart1(txd), uart0(rts), dev(ad14)
+mpp13 13   gpio, intr(out), dev(ad15)
+mpp14 14   gpio, i2c0(sck)
+mpp15 15   gpio, i2c0(sda)
+mpp16 16   gpo, dev(oe)
+mpp17 17   gpo, dev(clkout)
+mpp18 18   gpio, uart1(txd)
+mpp19 19   gpio, uart1(rxd), dev(rb)
+mpp20 20   gpo, dev(we0)
+mpp21 21   gpo, dev(ad0)
+mpp22 22   gpo, dev(ad1)
+mpp23 23   gpo, dev(ad2)
+mpp24 24   gpo, dev(ad3)
+mpp25 25   gpo, dev(ad4)
+mpp26 26   gpo, dev(ad5)
+mpp27 27   gpo, dev(ad6)
+mpp28 28   gpo, dev(ad7)
+mpp29 29   gpo, dev(a0)
+mpp30 30   gpo, dev(a1)
+mpp31 31   gpio, slv_smi(mdc), smi(mdc), dev(we1)
+mpp32 32   gpio, slv_smi(mdio), smi(mdio), dev(cs1)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c 
b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
index 63e1bd506983..61cbc138703e 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
@@ -38,6 +38,10 @@ enum armada_xp_variant {
V_MV78460   = BIT(2),
V_MV78230_PLUS  = (V_MV78230 | V_MV78260 | V_MV78460),
V_MV78260_PLUS  = (V_MV78260 | V_MV78460),
+   V_98DX3236  = BIT(3),
+   V_98DX3336  = BIT(4),
+   V_98DX4251  = BIT(5),
+   V_98DX3236_PLUS = (V_98DX3236 | V_98DX3336 | V_98DX4251),
 };
 
 static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
@@ -349,6 +353,131 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
 MPP_VAR_FUNCTION(0x1, "dev", "ad31",   V_MV78260_PLUS)),
 };
 
+static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = {
+   MPP_MODE(0,
+MPP_VAR_FUNCTION(0x0, "gpo", NULL,  V_98DX3236_PLUS),
+MPP_VAR_FUNCTION(0x2, "spi0", "mosi",   V_98DX3236_PLUS),
+MPP_VAR_FUNCTION(0x4, "dev", "ad8", V_98DX3236_PLUS)),
+   MPP_MODE(1,
+MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+MPP_VAR_FUNCTION(0x2, "spi0", "miso",   V_98DX3236_PLUS),
+MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
+   MPP_MODE(2,
+MPP_VAR_FUNCTION(0x0, "gpo", NULL,  V_98DX3236_PLUS),
+MPP_VAR_FUNCTION(0x2, "spi0", "sck",

[PATCHv5 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC

2017-01-26 Thread Chris Packham 
From: Kalyan Kinthada 

This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs
from Marvell.

Signed-off-by: Kalyan Kinthada 
Signed-off-by: Chris Packham 
Acked-by: Rob Herring 
Acked-by: Sebastian Hesselbarth 
---

Notes:
Changes in v2:
- include sdio support for the 98DX4251
Changes in v3:
- None
Changes in v4:
- Correct some discrepencies between binding and driver.
- Collect acks from Rob and Sebastian
Changes in v5:
- Update bindings to reflect "gpo" pins
- Use mvebu_mmio_mpp_ctrl instead of armada_xp_mpp_ctrl (note this is 
reliant
  on changes queued in linux-pinctrl)

 .../pinctrl/marvell,armada-98dx3236-pinctrl.txt|  46 ++
 drivers/pinctrl/mvebu/pinctrl-armada-xp.c  | 156 +
 2 files changed, 202 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt

diff --git 
a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
new file mode 100644
index ..97aef67ee769
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
@@ -0,0 +1,46 @@
+* Marvell 98dx3236 pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage
+
+Required properties:
+- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
+- reg: register specifier of MPP registers
+
+This driver supports all 98dx3236, 98dx3336 and 98dx4251 variants
+
+name  pins functions
+
+mpp0  0gpo, spi0(mosi), dev(ad8)
+mpp1  1gpio, spi0(miso), dev(ad9)
+mpp2  2gpo, spi0(sck), dev(ad10)
+mpp3  3gpio, spi0(cs0), dev(ad11)
+mpp4  4gpio, spi0(cs1), smi(mdc), dev(cs0)
+mpp5  5gpio, pex(rsto), sd0(cmd), dev(bootcs)
+mpp6  6gpo, sd0(clk), dev(a2)
+mpp7  7gpio, sd0(d0), dev(ale0)
+mpp8  8gpio, sd0(d1), dev(ale1)
+mpp9  9gpio, sd0(d2), dev(ready0)
+mpp10 10   gpio, sd0(d3), dev(ad12)
+mpp11 11   gpio, uart1(rxd), uart0(cts), dev(ad13)
+mpp12 12   gpo, uart1(txd), uart0(rts), dev(ad14)
+mpp13 13   gpio, intr(out), dev(ad15)
+mpp14 14   gpio, i2c0(sck)
+mpp15 15   gpio, i2c0(sda)
+mpp16 16   gpo, dev(oe)
+mpp17 17   gpo, dev(clkout)
+mpp18 18   gpio, uart1(txd)
+mpp19 19   gpio, uart1(rxd), dev(rb)
+mpp20 20   gpo, dev(we0)
+mpp21 21   gpo, dev(ad0)
+mpp22 22   gpo, dev(ad1)
+mpp23 23   gpo, dev(ad2)
+mpp24 24   gpo, dev(ad3)
+mpp25 25   gpo, dev(ad4)
+mpp26 26   gpo, dev(ad5)
+mpp27 27   gpo, dev(ad6)
+mpp28 28   gpo, dev(ad7)
+mpp29 29   gpo, dev(a0)
+mpp30 30   gpo, dev(a1)
+mpp31 31   gpio, slv_smi(mdc), smi(mdc), dev(we1)
+mpp32 32   gpio, slv_smi(mdio), smi(mdio), dev(cs1)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c 
b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
index 63e1bd506983..61cbc138703e 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
@@ -38,6 +38,10 @@ enum armada_xp_variant {
V_MV78460   = BIT(2),
V_MV78230_PLUS  = (V_MV78230 | V_MV78260 | V_MV78460),
V_MV78260_PLUS  = (V_MV78260 | V_MV78460),
+   V_98DX3236  = BIT(3),
+   V_98DX3336  = BIT(4),
+   V_98DX4251  = BIT(5),
+   V_98DX3236_PLUS = (V_98DX3236 | V_98DX3336 | V_98DX4251),
 };
 
 static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
@@ -349,6 +353,131 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
 MPP_VAR_FUNCTION(0x1, "dev", "ad31",   V_MV78260_PLUS)),
 };
 
+static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = {
+   MPP_MODE(0,
+MPP_VAR_FUNCTION(0x0, "gpo", NULL,  V_98DX3236_PLUS),
+MPP_VAR_FUNCTION(0x2, "spi0", "mosi",   V_98DX3236_PLUS),
+MPP_VAR_FUNCTION(0x4, "dev", "ad8", V_98DX3236_PLUS)),
+   MPP_MODE(1,
+MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+MPP_VAR_FUNCTION(0x2, "spi0", "miso",   V_98DX3236_PLUS),
+MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
+   MPP_MODE(2,
+MPP_VAR_FUNCTION(0x0, "gpo", NULL,  V_98DX3236_PLUS),
+MPP_VAR_FUNCTION(0x2, "spi0", "sck",V_98DX3236_PLUS),
+MPP_VAR_FUNCTION(0x4, "dev", "ad10",V_98DX3236_PLUS)),
+   MPP_MODE(3,
+MPP_VAR_FUNCTION(0x0, "gpio", NULL,