Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI

2017-09-30 Thread Alexey Kardashevskiy 
On 01/10/17 04:56, Jernej Škrabec wrote:
> Hi,
> 
> Dne sobota, 30. september 2017 ob 13:58:03 CEST je Alexey Kardashevskiy 
> napisal(a):
>> On 21/09/17 06:01, Jernej Skrabec wrote:
>>> [added media mailing list due to CEC question]
>>>
>>> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now,
>>> only video and CEC functionality is supported. Audio needs more tweaks.
>>>
>>> Series is based on the H3 DE2 patch series available on mailing list:
>>> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/522697.h
>>> tml (ignore patches marked with [NOT FOR REVIEW NOW] tag)
>>>
>>> Patch 1 adds support for polling plug detection since custom PHY used here
>>> doesn't support HPD interrupt.
>>>
>>> Patch 2 enables overflow workaround for v1.32a. This HDMI controller
>>> exhibits same issues as HDMI controller used in iMX6 SoCs.
>>>
>>> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.
>>>
>>> Patch 4 adds dt bindings documentation.
>>>
>>> Patch 5 adds actual H3 HDMI glue driver.
>>>
>>> Patch 6 and 7 add HDMI node to DT and enable it where needed.
>>>
>>> Allwinner used DW HDMI controller in a non standard way:
>>> - register offsets obfuscation layer, which can fortunately be turned off
>>> - register read lock, which has to be disabled by magic number
>>> - custom PHY, which have to be initialized before DW HDMI controller
>>> - non standard clocks
>>> - no HPD interrupt
>>>
>>> Because of that, I have two questions:
>>> - Since HPD have to be polled, is it enough just to enable poll mode? I'm
>>>
>>>   mainly concerned about invalidating CEC address here.
>>>
>>> - PHY has to be initialized before DW HDMI controller to disable offset
>>>
>>>   obfuscation and read lock among other things. This means that all clocks
>>>   have to be enabled in glue driver. This poses a problem, since when
>>>   using component model, dw-hdmi bridge uses drvdata for it's own private
>>>   data and prevents glue layer to pass a pointer to unbind function,
>>>   where clocks should be disabled. I noticed same issue in meson DW HDMI
>>>   glue driver, where clocks are also not disabled when unbind callback is
>>>   called. I noticed that when H3 SoC is shutdown, HDMI output is still
>>>   enabled and lastest image is shown on monitor until it is unplugged
>>>   from power supply. Is there any simple solution to this?
>>>
>>> Chen-Yu,
>>> TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I
>>> think it is safe to assume that divider in HDMI clock doesn't have any
>>> effect.
>>>
>>> Branch based on linux-next from 1. September with integrated patches is
>>> available here:
>>> https://github.com/jernejsk/linux-1/tree/h3_hdmi_rfc
>>
>> Out of curiosity I tried this one and got:
>>
>>
>>
>> [0.071711] sun4i-usb-phy 1c19400.phy: Couldn't request ID GPIO
>> [0.074809] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO
>> driver [0.076167] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi
>> PIO driver [0.148009] [ cut here ]
>> [0.148035] WARNING: CPU: 0 PID: 1 at
>> drivers/clk/sunxi-ng/ccu_common.c:41 ccu_nm_set_rate+0x1d0/0x274
>> [0.148046] CPU: 0 PID: 1 Comm: swapper/0 Not tainted
>> 4.13.0-rc6-next-20170825-aik-aik #24
>> [0.148051] Hardware name: Allwinner sun8i Family
>> [0.148082] [] (unwind_backtrace) from []
>> (show_stack+0x10/0x14)
>> [0.148101] [] (show_stack) from []
>> (dump_stack+0x84/0x98)
>> [0.148117] [] (dump_stack) from []
>> (__warn+0xe0/0xfc) [0.148132] [] (__warn) from []
>> (warn_slowpath_null+0x20/0x28)
>> [0.148145] [] (warn_slowpath_null) from []
>> (ccu_nm_set_rate+0x1d0/0x274)
>> [0.148161] [] (ccu_nm_set_rate) from []
>> (clk_change_rate+0x19c/0x250)
>> [0.148175] [] (clk_change_rate) from []
>> (clk_core_set_rate_nolock+0x68/0xb0)
>> [0.148187] [] (clk_core_set_rate_nolock) from []
>> (clk_set_rate+0x20/0x30)
>> [0.148202] [] (clk_set_rate) from []
>> (of_clk_set_defaults+0x200/0x364)
>> [0.148219] [] (of_clk_set_defaults) from []
>> (platform_drv_probe+0x18/0xb0)
>> [0.148233] [] (platform_drv_probe) from []
>> (driver_probe_device+0x234/0x2e8)
>> [0.148246] [] (driver_probe_device) from []
>> (__driver_attach+0xb8/0xbc)
>> [0.148258] [] (__driver_attach) from [> Unable to handle kernel NULL pointer dereference at virtual address 0008
>>
> 
> Patch for that is already merged upstream and can be found here:
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/
> drivers/clk/sunxi-ng?id=62d212bdb022deeb875f92f6e376c799e3f35eca

Lovely, it works, thanks!


>> and a bit later:
>>
>> [1.995572] Rebooting in 10 seconds..
> 
> I'm not sure about that one. Kernel config issue?



Yup, I did not have CMA enabled.




-- 
Alexey

Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI

2017-09-30 Thread Alexey Kardashevskiy 
On 01/10/17 04:56, Jernej Škrabec wrote:
> Hi,
> 
> Dne sobota, 30. september 2017 ob 13:58:03 CEST je Alexey Kardashevskiy 
> napisal(a):
>> On 21/09/17 06:01, Jernej Skrabec wrote:
>>> [added media mailing list due to CEC question]
>>>
>>> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now,
>>> only video and CEC functionality is supported. Audio needs more tweaks.
>>>
>>> Series is based on the H3 DE2 patch series available on mailing list:
>>> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/522697.h
>>> tml (ignore patches marked with [NOT FOR REVIEW NOW] tag)
>>>
>>> Patch 1 adds support for polling plug detection since custom PHY used here
>>> doesn't support HPD interrupt.
>>>
>>> Patch 2 enables overflow workaround for v1.32a. This HDMI controller
>>> exhibits same issues as HDMI controller used in iMX6 SoCs.
>>>
>>> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.
>>>
>>> Patch 4 adds dt bindings documentation.
>>>
>>> Patch 5 adds actual H3 HDMI glue driver.
>>>
>>> Patch 6 and 7 add HDMI node to DT and enable it where needed.
>>>
>>> Allwinner used DW HDMI controller in a non standard way:
>>> - register offsets obfuscation layer, which can fortunately be turned off
>>> - register read lock, which has to be disabled by magic number
>>> - custom PHY, which have to be initialized before DW HDMI controller
>>> - non standard clocks
>>> - no HPD interrupt
>>>
>>> Because of that, I have two questions:
>>> - Since HPD have to be polled, is it enough just to enable poll mode? I'm
>>>
>>>   mainly concerned about invalidating CEC address here.
>>>
>>> - PHY has to be initialized before DW HDMI controller to disable offset
>>>
>>>   obfuscation and read lock among other things. This means that all clocks
>>>   have to be enabled in glue driver. This poses a problem, since when
>>>   using component model, dw-hdmi bridge uses drvdata for it's own private
>>>   data and prevents glue layer to pass a pointer to unbind function,
>>>   where clocks should be disabled. I noticed same issue in meson DW HDMI
>>>   glue driver, where clocks are also not disabled when unbind callback is
>>>   called. I noticed that when H3 SoC is shutdown, HDMI output is still
>>>   enabled and lastest image is shown on monitor until it is unplugged
>>>   from power supply. Is there any simple solution to this?
>>>
>>> Chen-Yu,
>>> TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I
>>> think it is safe to assume that divider in HDMI clock doesn't have any
>>> effect.
>>>
>>> Branch based on linux-next from 1. September with integrated patches is
>>> available here:
>>> https://github.com/jernejsk/linux-1/tree/h3_hdmi_rfc
>>
>> Out of curiosity I tried this one and got:
>>
>>
>>
>> [0.071711] sun4i-usb-phy 1c19400.phy: Couldn't request ID GPIO
>> [0.074809] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO
>> driver [0.076167] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi
>> PIO driver [0.148009] [ cut here ]
>> [0.148035] WARNING: CPU: 0 PID: 1 at
>> drivers/clk/sunxi-ng/ccu_common.c:41 ccu_nm_set_rate+0x1d0/0x274
>> [0.148046] CPU: 0 PID: 1 Comm: swapper/0 Not tainted
>> 4.13.0-rc6-next-20170825-aik-aik #24
>> [0.148051] Hardware name: Allwinner sun8i Family
>> [0.148082] [] (unwind_backtrace) from []
>> (show_stack+0x10/0x14)
>> [0.148101] [] (show_stack) from []
>> (dump_stack+0x84/0x98)
>> [0.148117] [] (dump_stack) from []
>> (__warn+0xe0/0xfc) [0.148132] [] (__warn) from []
>> (warn_slowpath_null+0x20/0x28)
>> [0.148145] [] (warn_slowpath_null) from []
>> (ccu_nm_set_rate+0x1d0/0x274)
>> [0.148161] [] (ccu_nm_set_rate) from []
>> (clk_change_rate+0x19c/0x250)
>> [0.148175] [] (clk_change_rate) from []
>> (clk_core_set_rate_nolock+0x68/0xb0)
>> [0.148187] [] (clk_core_set_rate_nolock) from []
>> (clk_set_rate+0x20/0x30)
>> [0.148202] [] (clk_set_rate) from []
>> (of_clk_set_defaults+0x200/0x364)
>> [0.148219] [] (of_clk_set_defaults) from []
>> (platform_drv_probe+0x18/0xb0)
>> [0.148233] [] (platform_drv_probe) from []
>> (driver_probe_device+0x234/0x2e8)
>> [0.148246] [] (driver_probe_device) from []
>> (__driver_attach+0xb8/0xbc)
>> [0.148258] [] (__driver_attach) from [> Unable to handle kernel NULL pointer dereference at virtual address 0008
>>
> 
> Patch for that is already merged upstream and can be found here:
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/
> drivers/clk/sunxi-ng?id=62d212bdb022deeb875f92f6e376c799e3f35eca

Lovely, it works, thanks!


>> and a bit later:
>>
>> [1.995572] Rebooting in 10 seconds..
> 
> I'm not sure about that one. Kernel config issue?



Yup, I did not have CMA enabled.




-- 
Alexey

Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI

2017-09-30 Thread Jernej Škrabec 
Hi,

Dne sobota, 30. september 2017 ob 13:58:03 CEST je Alexey Kardashevskiy 
napisal(a):
> On 21/09/17 06:01, Jernej Skrabec wrote:
> > [added media mailing list due to CEC question]
> > 
> > This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now,
> > only video and CEC functionality is supported. Audio needs more tweaks.
> > 
> > Series is based on the H3 DE2 patch series available on mailing list:
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/522697.h
> > tml (ignore patches marked with [NOT FOR REVIEW NOW] tag)
> > 
> > Patch 1 adds support for polling plug detection since custom PHY used here
> > doesn't support HPD interrupt.
> > 
> > Patch 2 enables overflow workaround for v1.32a. This HDMI controller
> > exhibits same issues as HDMI controller used in iMX6 SoCs.
> > 
> > Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.
> > 
> > Patch 4 adds dt bindings documentation.
> > 
> > Patch 5 adds actual H3 HDMI glue driver.
> > 
> > Patch 6 and 7 add HDMI node to DT and enable it where needed.
> > 
> > Allwinner used DW HDMI controller in a non standard way:
> > - register offsets obfuscation layer, which can fortunately be turned off
> > - register read lock, which has to be disabled by magic number
> > - custom PHY, which have to be initialized before DW HDMI controller
> > - non standard clocks
> > - no HPD interrupt
> > 
> > Because of that, I have two questions:
> > - Since HPD have to be polled, is it enough just to enable poll mode? I'm
> > 
> >   mainly concerned about invalidating CEC address here.
> > 
> > - PHY has to be initialized before DW HDMI controller to disable offset
> > 
> >   obfuscation and read lock among other things. This means that all clocks
> >   have to be enabled in glue driver. This poses a problem, since when
> >   using component model, dw-hdmi bridge uses drvdata for it's own private
> >   data and prevents glue layer to pass a pointer to unbind function,
> >   where clocks should be disabled. I noticed same issue in meson DW HDMI
> >   glue driver, where clocks are also not disabled when unbind callback is
> >   called. I noticed that when H3 SoC is shutdown, HDMI output is still
> >   enabled and lastest image is shown on monitor until it is unplugged
> >   from power supply. Is there any simple solution to this?
> > 
> > Chen-Yu,
> > TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I
> > think it is safe to assume that divider in HDMI clock doesn't have any
> > effect.
> > 
> > Branch based on linux-next from 1. September with integrated patches is
> > available here:
> > https://github.com/jernejsk/linux-1/tree/h3_hdmi_rfc
> 
> Out of curiosity I tried this one and got:
> 
> 
> 
> [0.071711] sun4i-usb-phy 1c19400.phy: Couldn't request ID GPIO
> [0.074809] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO
> driver [0.076167] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi
> PIO driver [0.148009] [ cut here ]
> [0.148035] WARNING: CPU: 0 PID: 1 at
> drivers/clk/sunxi-ng/ccu_common.c:41 ccu_nm_set_rate+0x1d0/0x274
> [0.148046] CPU: 0 PID: 1 Comm: swapper/0 Not tainted
> 4.13.0-rc6-next-20170825-aik-aik #24
> [0.148051] Hardware name: Allwinner sun8i Family
> [0.148082] [] (unwind_backtrace) from []
> (show_stack+0x10/0x14)
> [0.148101] [] (show_stack) from []
> (dump_stack+0x84/0x98)
> [0.148117] [] (dump_stack) from []
> (__warn+0xe0/0xfc) [0.148132] [] (__warn) from []
> (warn_slowpath_null+0x20/0x28)
> [0.148145] [] (warn_slowpath_null) from []
> (ccu_nm_set_rate+0x1d0/0x274)
> [0.148161] [] (ccu_nm_set_rate) from []
> (clk_change_rate+0x19c/0x250)
> [0.148175] [] (clk_change_rate) from []
> (clk_core_set_rate_nolock+0x68/0xb0)
> [0.148187] [] (clk_core_set_rate_nolock) from []
> (clk_set_rate+0x20/0x30)
> [0.148202] [] (clk_set_rate) from []
> (of_clk_set_defaults+0x200/0x364)
> [0.148219] [] (of_clk_set_defaults) from []
> (platform_drv_probe+0x18/0xb0)
> [0.148233] [] (platform_drv_probe) from []
> (driver_probe_device+0x234/0x2e8)
> [0.148246] [] (driver_probe_device) from []
> (__driver_attach+0xb8/0xbc)
> [0.148258] [] (__driver_attach) from [ Unable to handle kernel NULL pointer dereference at virtual address 0008
> 

Patch for that is already merged upstream and can be found here:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/
drivers/clk/sunxi-ng?id=62d212bdb022deeb875f92f6e376c799e3f35eca

> and a bit later:
> 
> [1.995572] Rebooting in 10 seconds..

I'm not sure about that one. Kernel config issue?

Regards,
Jernej

> 
> Orange PI PC, script.bin.OPI-PC_1080p60_hdmi.
> 
> What do I miss? Thanks.
> 
> 
> 
> --
> Alexey

Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI

2017-09-30 Thread Jernej Škrabec 
Hi,

Dne sobota, 30. september 2017 ob 13:58:03 CEST je Alexey Kardashevskiy 
napisal(a):
> On 21/09/17 06:01, Jernej Skrabec wrote:
> > [added media mailing list due to CEC question]
> > 
> > This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now,
> > only video and CEC functionality is supported. Audio needs more tweaks.
> > 
> > Series is based on the H3 DE2 patch series available on mailing list:
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/522697.h
> > tml (ignore patches marked with [NOT FOR REVIEW NOW] tag)
> > 
> > Patch 1 adds support for polling plug detection since custom PHY used here
> > doesn't support HPD interrupt.
> > 
> > Patch 2 enables overflow workaround for v1.32a. This HDMI controller
> > exhibits same issues as HDMI controller used in iMX6 SoCs.
> > 
> > Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.
> > 
> > Patch 4 adds dt bindings documentation.
> > 
> > Patch 5 adds actual H3 HDMI glue driver.
> > 
> > Patch 6 and 7 add HDMI node to DT and enable it where needed.
> > 
> > Allwinner used DW HDMI controller in a non standard way:
> > - register offsets obfuscation layer, which can fortunately be turned off
> > - register read lock, which has to be disabled by magic number
> > - custom PHY, which have to be initialized before DW HDMI controller
> > - non standard clocks
> > - no HPD interrupt
> > 
> > Because of that, I have two questions:
> > - Since HPD have to be polled, is it enough just to enable poll mode? I'm
> > 
> >   mainly concerned about invalidating CEC address here.
> > 
> > - PHY has to be initialized before DW HDMI controller to disable offset
> > 
> >   obfuscation and read lock among other things. This means that all clocks
> >   have to be enabled in glue driver. This poses a problem, since when
> >   using component model, dw-hdmi bridge uses drvdata for it's own private
> >   data and prevents glue layer to pass a pointer to unbind function,
> >   where clocks should be disabled. I noticed same issue in meson DW HDMI
> >   glue driver, where clocks are also not disabled when unbind callback is
> >   called. I noticed that when H3 SoC is shutdown, HDMI output is still
> >   enabled and lastest image is shown on monitor until it is unplugged
> >   from power supply. Is there any simple solution to this?
> > 
> > Chen-Yu,
> > TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I
> > think it is safe to assume that divider in HDMI clock doesn't have any
> > effect.
> > 
> > Branch based on linux-next from 1. September with integrated patches is
> > available here:
> > https://github.com/jernejsk/linux-1/tree/h3_hdmi_rfc
> 
> Out of curiosity I tried this one and got:
> 
> 
> 
> [0.071711] sun4i-usb-phy 1c19400.phy: Couldn't request ID GPIO
> [0.074809] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO
> driver [0.076167] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi
> PIO driver [0.148009] [ cut here ]
> [0.148035] WARNING: CPU: 0 PID: 1 at
> drivers/clk/sunxi-ng/ccu_common.c:41 ccu_nm_set_rate+0x1d0/0x274
> [0.148046] CPU: 0 PID: 1 Comm: swapper/0 Not tainted
> 4.13.0-rc6-next-20170825-aik-aik #24
> [0.148051] Hardware name: Allwinner sun8i Family
> [0.148082] [] (unwind_backtrace) from []
> (show_stack+0x10/0x14)
> [0.148101] [] (show_stack) from []
> (dump_stack+0x84/0x98)
> [0.148117] [] (dump_stack) from []
> (__warn+0xe0/0xfc) [0.148132] [] (__warn) from []
> (warn_slowpath_null+0x20/0x28)
> [0.148145] [] (warn_slowpath_null) from []
> (ccu_nm_set_rate+0x1d0/0x274)
> [0.148161] [] (ccu_nm_set_rate) from []
> (clk_change_rate+0x19c/0x250)
> [0.148175] [] (clk_change_rate) from []
> (clk_core_set_rate_nolock+0x68/0xb0)
> [0.148187] [] (clk_core_set_rate_nolock) from []
> (clk_set_rate+0x20/0x30)
> [0.148202] [] (clk_set_rate) from []
> (of_clk_set_defaults+0x200/0x364)
> [0.148219] [] (of_clk_set_defaults) from []
> (platform_drv_probe+0x18/0xb0)
> [0.148233] [] (platform_drv_probe) from []
> (driver_probe_device+0x234/0x2e8)
> [0.148246] [] (driver_probe_device) from []
> (__driver_attach+0xb8/0xbc)
> [0.148258] [] (__driver_attach) from [ Unable to handle kernel NULL pointer dereference at virtual address 0008
> 

Patch for that is already merged upstream and can be found here:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/
drivers/clk/sunxi-ng?id=62d212bdb022deeb875f92f6e376c799e3f35eca

> and a bit later:
> 
> [1.995572] Rebooting in 10 seconds..

I'm not sure about that one. Kernel config issue?

Regards,
Jernej

> 
> Orange PI PC, script.bin.OPI-PC_1080p60_hdmi.
> 
> What do I miss? Thanks.
> 
> 
> 
> --
> Alexey

Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI

2017-09-30 Thread Alexey Kardashevskiy 
On 21/09/17 06:01, Jernej Skrabec wrote:
> [added media mailing list due to CEC question]
> 
> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only
> video and CEC functionality is supported. Audio needs more tweaks.
> 
> Series is based on the H3 DE2 patch series available on mailing list:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/522697.html
> (ignore patches marked with [NOT FOR REVIEW NOW] tag)
> 
> Patch 1 adds support for polling plug detection since custom PHY used here
> doesn't support HPD interrupt.
> 
> Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits
> same issues as HDMI controller used in iMX6 SoCs.
> 
> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.
> 
> Patch 4 adds dt bindings documentation.
> 
> Patch 5 adds actual H3 HDMI glue driver.
> 
> Patch 6 and 7 add HDMI node to DT and enable it where needed.
> 
> Allwinner used DW HDMI controller in a non standard way:
> - register offsets obfuscation layer, which can fortunately be turned off
> - register read lock, which has to be disabled by magic number
> - custom PHY, which have to be initialized before DW HDMI controller
> - non standard clocks
> - no HPD interrupt
> 
> Because of that, I have two questions:
> - Since HPD have to be polled, is it enough just to enable poll mode? I'm
>   mainly concerned about invalidating CEC address here.
> - PHY has to be initialized before DW HDMI controller to disable offset
>   obfuscation and read lock among other things. This means that all clocks 
> have
>   to be enabled in glue driver. This poses a problem, since when using
>   component model, dw-hdmi bridge uses drvdata for it's own private data and
>   prevents glue layer to pass a pointer to unbind function, where clocks 
> should
>   be disabled. I noticed same issue in meson DW HDMI glue driver, where clocks
>   are also not disabled when unbind callback is called. I noticed that when H3
>   SoC is shutdown, HDMI output is still enabled and lastest image is shown on
>   monitor until it is unplugged from power supply. Is there any simple 
> solution
>   to this?
> 
> Chen-Yu,
> TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I 
> think
> it is safe to assume that divider in HDMI clock doesn't have any effect.
> 
> Branch based on linux-next from 1. September with integrated patches is
> available here:
> https://github.com/jernejsk/linux-1/tree/h3_hdmi_rfc


Out of curiosity I tried this one and got:



[0.071711] sun4i-usb-phy 1c19400.phy: Couldn't request ID GPIO
[0.074809] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO driver
[0.076167] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi PIO driver
[0.148009] [ cut here ]
[0.148035] WARNING: CPU: 0 PID: 1 at
drivers/clk/sunxi-ng/ccu_common.c:41 ccu_nm_set_rate+0x1d0/0x274
[0.148046] CPU: 0 PID: 1 Comm: swapper/0 Not tainted
4.13.0-rc6-next-20170825-aik-aik #24
[0.148051] Hardware name: Allwinner sun8i Family
[0.148082] [] (unwind_backtrace) from []
(show_stack+0x10/0x14)
[0.148101] [] (show_stack) from []
(dump_stack+0x84/0x98)
[0.148117] [] (dump_stack) from [] (__warn+0xe0/0xfc)
[0.148132] [] (__warn) from []
(warn_slowpath_null+0x20/0x28)
[0.148145] [] (warn_slowpath_null) from []
(ccu_nm_set_rate+0x1d0/0x274)
[0.148161] [] (ccu_nm_set_rate) from []
(clk_change_rate+0x19c/0x250)
[0.148175] [] (clk_change_rate) from []
(clk_core_set_rate_nolock+0x68/0xb0)
[0.148187] [] (clk_core_set_rate_nolock) from []
(clk_set_rate+0x20/0x30)
[0.148202] [] (clk_set_rate) from []
(of_clk_set_defaults+0x200/0x364)
[0.148219] [] (of_clk_set_defaults) from []
(platform_drv_probe+0x18/0xb0)
[0.148233] [] (platform_drv_probe) from []
(driver_probe_device+0x234/0x2e8)
[0.148246] [] (driver_probe_device) from []
(__driver_attach+0xb8/0xbc)
[0.148258] [] (__driver_attach) from [

Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI

2017-09-30 Thread Alexey Kardashevskiy 
On 21/09/17 06:01, Jernej Skrabec wrote:
> [added media mailing list due to CEC question]
> 
> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only
> video and CEC functionality is supported. Audio needs more tweaks.
> 
> Series is based on the H3 DE2 patch series available on mailing list:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/522697.html
> (ignore patches marked with [NOT FOR REVIEW NOW] tag)
> 
> Patch 1 adds support for polling plug detection since custom PHY used here
> doesn't support HPD interrupt.
> 
> Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits
> same issues as HDMI controller used in iMX6 SoCs.
> 
> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.
> 
> Patch 4 adds dt bindings documentation.
> 
> Patch 5 adds actual H3 HDMI glue driver.
> 
> Patch 6 and 7 add HDMI node to DT and enable it where needed.
> 
> Allwinner used DW HDMI controller in a non standard way:
> - register offsets obfuscation layer, which can fortunately be turned off
> - register read lock, which has to be disabled by magic number
> - custom PHY, which have to be initialized before DW HDMI controller
> - non standard clocks
> - no HPD interrupt
> 
> Because of that, I have two questions:
> - Since HPD have to be polled, is it enough just to enable poll mode? I'm
>   mainly concerned about invalidating CEC address here.
> - PHY has to be initialized before DW HDMI controller to disable offset
>   obfuscation and read lock among other things. This means that all clocks 
> have
>   to be enabled in glue driver. This poses a problem, since when using
>   component model, dw-hdmi bridge uses drvdata for it's own private data and
>   prevents glue layer to pass a pointer to unbind function, where clocks 
> should
>   be disabled. I noticed same issue in meson DW HDMI glue driver, where clocks
>   are also not disabled when unbind callback is called. I noticed that when H3
>   SoC is shutdown, HDMI output is still enabled and lastest image is shown on
>   monitor until it is unplugged from power supply. Is there any simple 
> solution
>   to this?
> 
> Chen-Yu,
> TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I 
> think
> it is safe to assume that divider in HDMI clock doesn't have any effect.
> 
> Branch based on linux-next from 1. September with integrated patches is
> available here:
> https://github.com/jernejsk/linux-1/tree/h3_hdmi_rfc


Out of curiosity I tried this one and got:



[0.071711] sun4i-usb-phy 1c19400.phy: Couldn't request ID GPIO
[0.074809] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO driver
[0.076167] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi PIO driver
[0.148009] [ cut here ]
[0.148035] WARNING: CPU: 0 PID: 1 at
drivers/clk/sunxi-ng/ccu_common.c:41 ccu_nm_set_rate+0x1d0/0x274
[0.148046] CPU: 0 PID: 1 Comm: swapper/0 Not tainted
4.13.0-rc6-next-20170825-aik-aik #24
[0.148051] Hardware name: Allwinner sun8i Family
[0.148082] [] (unwind_backtrace) from []
(show_stack+0x10/0x14)
[0.148101] [] (show_stack) from []
(dump_stack+0x84/0x98)
[0.148117] [] (dump_stack) from [] (__warn+0xe0/0xfc)
[0.148132] [] (__warn) from []
(warn_slowpath_null+0x20/0x28)
[0.148145] [] (warn_slowpath_null) from []
(ccu_nm_set_rate+0x1d0/0x274)
[0.148161] [] (ccu_nm_set_rate) from []
(clk_change_rate+0x19c/0x250)
[0.148175] [] (clk_change_rate) from []
(clk_core_set_rate_nolock+0x68/0xb0)
[0.148187] [] (clk_core_set_rate_nolock) from []
(clk_set_rate+0x20/0x30)
[0.148202] [] (clk_set_rate) from []
(of_clk_set_defaults+0x200/0x364)
[0.148219] [] (of_clk_set_defaults) from []
(platform_drv_probe+0x18/0xb0)
[0.148233] [] (platform_drv_probe) from []
(driver_probe_device+0x234/0x2e8)
[0.148246] [] (driver_probe_device) from []
(__driver_attach+0xb8/0xbc)
[0.148258] [] (__driver_attach) from [

Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI

2017-09-21 Thread Hans Verkuil 
On 09/21/17 11:39, Jose Abreu wrote:
> Hi Jernej,
> 
> On 20-09-2017 21:01, Jernej Skrabec wrote:
>> [added media mailing list due to CEC question]
>>
>> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only
>> video and CEC functionality is supported. Audio needs more tweaks.
>>
>> Series is based on the H3 DE2 patch series available on mailing list:
>> https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Darm-2Dkernel_2017-2DAugust_522697.html=DwIBAg=DPL6_X_6JkXFx7AXWqB0tg=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4=JCFaMXK1MmZ3jE745_YcqZhZkaqtc6UapGfSSapcz_s=
>>  
>> (ignore patches marked with [NOT FOR REVIEW NOW] tag)
>>
>> Patch 1 adds support for polling plug detection since custom PHY used here
>> doesn't support HPD interrupt.
>>
>> Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits
>> same issues as HDMI controller used in iMX6 SoCs.
>>
>> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.
>>
>> Patch 4 adds dt bindings documentation.
>>
>> Patch 5 adds actual H3 HDMI glue driver.
>>
>> Patch 6 and 7 add HDMI node to DT and enable it where needed.
>>
>> Allwinner used DW HDMI controller in a non standard way:
>> - register offsets obfuscation layer, which can fortunately be turned off
>> - register read lock, which has to be disabled by magic number
>> - custom PHY, which have to be initialized before DW HDMI controller
>> - non standard clocks
>> - no HPD interrupt
>>
>> Because of that, I have two questions:
>> - Since HPD have to be polled, is it enough just to enable poll mode? I'm
>>   mainly concerned about invalidating CEC address here.
> 
> You mean you get no interrupt when HPD status changes? Hans can
> answer this better but then you will need to invalidate the cec
> physical address yourself because right now its invalidated in
> the dw-hdmi irq handler (see dw_hdmi_irq()).

That's correct. When the HPD goes low you need to call 
cec_notifier_phys_addr_invalidate()
to invalidate the physical address. This is not terribly time sensitive, i.e.
checking this once a second would be quick enough.

Regards,

Hans

Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI

2017-09-21 Thread Hans Verkuil 
On 09/21/17 11:39, Jose Abreu wrote:
> Hi Jernej,
> 
> On 20-09-2017 21:01, Jernej Skrabec wrote:
>> [added media mailing list due to CEC question]
>>
>> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only
>> video and CEC functionality is supported. Audio needs more tweaks.
>>
>> Series is based on the H3 DE2 patch series available on mailing list:
>> https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Darm-2Dkernel_2017-2DAugust_522697.html=DwIBAg=DPL6_X_6JkXFx7AXWqB0tg=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4=JCFaMXK1MmZ3jE745_YcqZhZkaqtc6UapGfSSapcz_s=
>>  
>> (ignore patches marked with [NOT FOR REVIEW NOW] tag)
>>
>> Patch 1 adds support for polling plug detection since custom PHY used here
>> doesn't support HPD interrupt.
>>
>> Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits
>> same issues as HDMI controller used in iMX6 SoCs.
>>
>> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.
>>
>> Patch 4 adds dt bindings documentation.
>>
>> Patch 5 adds actual H3 HDMI glue driver.
>>
>> Patch 6 and 7 add HDMI node to DT and enable it where needed.
>>
>> Allwinner used DW HDMI controller in a non standard way:
>> - register offsets obfuscation layer, which can fortunately be turned off
>> - register read lock, which has to be disabled by magic number
>> - custom PHY, which have to be initialized before DW HDMI controller
>> - non standard clocks
>> - no HPD interrupt
>>
>> Because of that, I have two questions:
>> - Since HPD have to be polled, is it enough just to enable poll mode? I'm
>>   mainly concerned about invalidating CEC address here.
> 
> You mean you get no interrupt when HPD status changes? Hans can
> answer this better but then you will need to invalidate the cec
> physical address yourself because right now its invalidated in
> the dw-hdmi irq handler (see dw_hdmi_irq()).

That's correct. When the HPD goes low you need to call 
cec_notifier_phys_addr_invalidate()
to invalidate the physical address. This is not terribly time sensitive, i.e.
checking this once a second would be quick enough.

Regards,

Hans

Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI

2017-09-21 Thread Jose Abreu 
Hi Jernej,

On 20-09-2017 21:01, Jernej Skrabec wrote:
> [added media mailing list due to CEC question]
>
> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only
> video and CEC functionality is supported. Audio needs more tweaks.
>
> Series is based on the H3 DE2 patch series available on mailing list:
> https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Darm-2Dkernel_2017-2DAugust_522697.html=DwIBAg=DPL6_X_6JkXFx7AXWqB0tg=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4=JCFaMXK1MmZ3jE745_YcqZhZkaqtc6UapGfSSapcz_s=
>  
> (ignore patches marked with [NOT FOR REVIEW NOW] tag)
>
> Patch 1 adds support for polling plug detection since custom PHY used here
> doesn't support HPD interrupt.
>
> Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits
> same issues as HDMI controller used in iMX6 SoCs.
>
> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.
>
> Patch 4 adds dt bindings documentation.
>
> Patch 5 adds actual H3 HDMI glue driver.
>
> Patch 6 and 7 add HDMI node to DT and enable it where needed.
>
> Allwinner used DW HDMI controller in a non standard way:
> - register offsets obfuscation layer, which can fortunately be turned off
> - register read lock, which has to be disabled by magic number
> - custom PHY, which have to be initialized before DW HDMI controller
> - non standard clocks
> - no HPD interrupt
>
> Because of that, I have two questions:
> - Since HPD have to be polled, is it enough just to enable poll mode? I'm
>   mainly concerned about invalidating CEC address here.

You mean you get no interrupt when HPD status changes? Hans can
answer this better but then you will need to invalidate the cec
physical address yourself because right now its invalidated in
the dw-hdmi irq handler (see dw_hdmi_irq()).

> - PHY has to be initialized before DW HDMI controller to disable offset
>   obfuscation and read lock among other things. This means that all clocks 
> have
>   to be enabled in glue driver. This poses a problem, since when using
>   component model, dw-hdmi bridge uses drvdata for it's own private data and
>   prevents glue layer to pass a pointer to unbind function, where clocks 
> should
>   be disabled. I noticed same issue in meson DW HDMI glue driver, where clocks
>   are also not disabled when unbind callback is called. I noticed that when H3
>   SoC is shutdown, HDMI output is still enabled and lastest image is shown on
>   monitor until it is unplugged from power supply. Is there any simple 
> solution
>   to this?

I don't know if you can use an empty platform device created with
platform_device_alloc(). Perhaps it would be better fix this in
the dw-hdmi driver. I see two solutions:

- Either you return the dw-hdmi private structure in the bind
callback, store it and pass it in the unbind
- Or, you pass your own private data to the dw-hdmi bind, the
dw-hdmi stores it and you just create a public function in the
dw-hdmi driver called like dw_hdmi_get_auxdata(struct device
*dev) which returns your private data.

I think first option is nice, maybe anyone else can suggest
something better?

Best regards,
Jose Miguel Abreu

>
> Chen-Yu,
> TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I 
> think
> it is safe to assume that divider in HDMI clock doesn't have any effect.
>
> Branch based on linux-next from 1. September with integrated patches is
> available here:
> https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_jernejsk_linux-2D1_tree_h3-5Fhdmi-5Frfc=DwIBAg=DPL6_X_6JkXFx7AXWqB0tg=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4=lDAnd3egsc2sxqVM-Ya_Me9ozWXKWvxxvsdV3Jn3vpA=
>  
>
> Some additonal info about H3 HDMI:
> https://urldefense.proofpoint.com/v2/url?u=https-3A__linux-2Dsunxi.org_DWC-5FHDMI-5FController=DwIBAg=DPL6_X_6JkXFx7AXWqB0tg=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4=d9iEgk23RCLJL4oXJ4kkt6NyYK90_vFy0mCD3WauJDk=
>  
>
> Thanks to Jens Kuske, who figured out that it is actually DW HDMI controller
> and mapped scrambled register offsets to original ones.
>
> Icenowy Zheng (1):
>   ARM: sun8i: h3: Add DesignWare HDMI controller node
>
> Jernej Skrabec (6):
>   drm: bridge: Enable polling hpd event in dw_hdmi
>   drm: bridge: Enable workaround in dw_hdmi for v1.32a
>   clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
>   dt-bindings: Document Allwinner DWC HDMI TX node
>   drm: sun4i: Add a glue for the DesignWare HDMI controller in H3
>   ARM: sun8i: h3: Enable HDMI output on H3 boards
>
>  .../bindings/display/sunxi/sun4i-drm.txt   | 158 ++-
>  arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts|  33 ++
>  arch/arm/boot/dts/sun8i-h3-beelink-x2.dts  |  33 ++
>  arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts   |  33 ++
>  arch/arm/boot/dts/sun8i-h3-orangepi-2.dts  |  33 ++
>

Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI

2017-09-21 Thread Jose Abreu 
Hi Jernej,

On 20-09-2017 21:01, Jernej Skrabec wrote:
> [added media mailing list due to CEC question]
>
> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only
> video and CEC functionality is supported. Audio needs more tweaks.
>
> Series is based on the H3 DE2 patch series available on mailing list:
> https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Darm-2Dkernel_2017-2DAugust_522697.html=DwIBAg=DPL6_X_6JkXFx7AXWqB0tg=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4=JCFaMXK1MmZ3jE745_YcqZhZkaqtc6UapGfSSapcz_s=
>  
> (ignore patches marked with [NOT FOR REVIEW NOW] tag)
>
> Patch 1 adds support for polling plug detection since custom PHY used here
> doesn't support HPD interrupt.
>
> Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits
> same issues as HDMI controller used in iMX6 SoCs.
>
> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.
>
> Patch 4 adds dt bindings documentation.
>
> Patch 5 adds actual H3 HDMI glue driver.
>
> Patch 6 and 7 add HDMI node to DT and enable it where needed.
>
> Allwinner used DW HDMI controller in a non standard way:
> - register offsets obfuscation layer, which can fortunately be turned off
> - register read lock, which has to be disabled by magic number
> - custom PHY, which have to be initialized before DW HDMI controller
> - non standard clocks
> - no HPD interrupt
>
> Because of that, I have two questions:
> - Since HPD have to be polled, is it enough just to enable poll mode? I'm
>   mainly concerned about invalidating CEC address here.

You mean you get no interrupt when HPD status changes? Hans can
answer this better but then you will need to invalidate the cec
physical address yourself because right now its invalidated in
the dw-hdmi irq handler (see dw_hdmi_irq()).

> - PHY has to be initialized before DW HDMI controller to disable offset
>   obfuscation and read lock among other things. This means that all clocks 
> have
>   to be enabled in glue driver. This poses a problem, since when using
>   component model, dw-hdmi bridge uses drvdata for it's own private data and
>   prevents glue layer to pass a pointer to unbind function, where clocks 
> should
>   be disabled. I noticed same issue in meson DW HDMI glue driver, where clocks
>   are also not disabled when unbind callback is called. I noticed that when H3
>   SoC is shutdown, HDMI output is still enabled and lastest image is shown on
>   monitor until it is unplugged from power supply. Is there any simple 
> solution
>   to this?

I don't know if you can use an empty platform device created with
platform_device_alloc(). Perhaps it would be better fix this in
the dw-hdmi driver. I see two solutions:

- Either you return the dw-hdmi private structure in the bind
callback, store it and pass it in the unbind
- Or, you pass your own private data to the dw-hdmi bind, the
dw-hdmi stores it and you just create a public function in the
dw-hdmi driver called like dw_hdmi_get_auxdata(struct device
*dev) which returns your private data.

I think first option is nice, maybe anyone else can suggest
something better?

Best regards,
Jose Miguel Abreu

>
> Chen-Yu,
> TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I 
> think
> it is safe to assume that divider in HDMI clock doesn't have any effect.
>
> Branch based on linux-next from 1. September with integrated patches is
> available here:
> https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_jernejsk_linux-2D1_tree_h3-5Fhdmi-5Frfc=DwIBAg=DPL6_X_6JkXFx7AXWqB0tg=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4=lDAnd3egsc2sxqVM-Ya_Me9ozWXKWvxxvsdV3Jn3vpA=
>  
>
> Some additonal info about H3 HDMI:
> https://urldefense.proofpoint.com/v2/url?u=https-3A__linux-2Dsunxi.org_DWC-5FHDMI-5FController=DwIBAg=DPL6_X_6JkXFx7AXWqB0tg=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4=d9iEgk23RCLJL4oXJ4kkt6NyYK90_vFy0mCD3WauJDk=
>  
>
> Thanks to Jens Kuske, who figured out that it is actually DW HDMI controller
> and mapped scrambled register offsets to original ones.
>
> Icenowy Zheng (1):
>   ARM: sun8i: h3: Add DesignWare HDMI controller node
>
> Jernej Skrabec (6):
>   drm: bridge: Enable polling hpd event in dw_hdmi
>   drm: bridge: Enable workaround in dw_hdmi for v1.32a
>   clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
>   dt-bindings: Document Allwinner DWC HDMI TX node
>   drm: sun4i: Add a glue for the DesignWare HDMI controller in H3
>   ARM: sun8i: h3: Enable HDMI output on H3 boards
>
>  .../bindings/display/sunxi/sun4i-drm.txt   | 158 ++-
>  arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts|  33 ++
>  arch/arm/boot/dts/sun8i-h3-beelink-x2.dts  |  33 ++
>  arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts   |  33 ++
>  arch/arm/boot/dts/sun8i-h3-orangepi-2.dts  |  33 ++
>

[RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI

2017-09-20 Thread Jernej Skrabec 
[added media mailing list due to CEC question]

This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only
video and CEC functionality is supported. Audio needs more tweaks.

Series is based on the H3 DE2 patch series available on mailing list:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/522697.html
(ignore patches marked with [NOT FOR REVIEW NOW] tag)

Patch 1 adds support for polling plug detection since custom PHY used here
doesn't support HPD interrupt.

Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits
same issues as HDMI controller used in iMX6 SoCs.

Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.

Patch 4 adds dt bindings documentation.

Patch 5 adds actual H3 HDMI glue driver.

Patch 6 and 7 add HDMI node to DT and enable it where needed.

Allwinner used DW HDMI controller in a non standard way:
- register offsets obfuscation layer, which can fortunately be turned off
- register read lock, which has to be disabled by magic number
- custom PHY, which have to be initialized before DW HDMI controller
- non standard clocks
- no HPD interrupt

Because of that, I have two questions:
- Since HPD have to be polled, is it enough just to enable poll mode? I'm
  mainly concerned about invalidating CEC address here.
- PHY has to be initialized before DW HDMI controller to disable offset
  obfuscation and read lock among other things. This means that all clocks have
  to be enabled in glue driver. This poses a problem, since when using
  component model, dw-hdmi bridge uses drvdata for it's own private data and
  prevents glue layer to pass a pointer to unbind function, where clocks should
  be disabled. I noticed same issue in meson DW HDMI glue driver, where clocks
  are also not disabled when unbind callback is called. I noticed that when H3
  SoC is shutdown, HDMI output is still enabled and lastest image is shown on
  monitor until it is unplugged from power supply. Is there any simple solution
  to this?

Chen-Yu,
TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I think
it is safe to assume that divider in HDMI clock doesn't have any effect.

Branch based on linux-next from 1. September with integrated patches is
available here:
https://github.com/jernejsk/linux-1/tree/h3_hdmi_rfc

Some additonal info about H3 HDMI:
https://linux-sunxi.org/DWC_HDMI_Controller

Thanks to Jens Kuske, who figured out that it is actually DW HDMI controller
and mapped scrambled register offsets to original ones.

Icenowy Zheng (1):
  ARM: sun8i: h3: Add DesignWare HDMI controller node

Jernej Skrabec (6):
  drm: bridge: Enable polling hpd event in dw_hdmi
  drm: bridge: Enable workaround in dw_hdmi for v1.32a
  clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
  dt-bindings: Document Allwinner DWC HDMI TX node
  drm: sun4i: Add a glue for the DesignWare HDMI controller in H3
  ARM: sun8i: h3: Enable HDMI output on H3 boards

 .../bindings/display/sunxi/sun4i-drm.txt   | 158 ++-
 arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts|  33 ++
 arch/arm/boot/dts/sun8i-h3-beelink-x2.dts  |  33 ++
 arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts   |  33 ++
 arch/arm/boot/dts/sun8i-h3-orangepi-2.dts  |  33 ++
 arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts   |  33 ++
 arch/arm/boot/dts/sun8i-h3-orangepi-one.dts|  33 ++
 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts |  33 ++
 arch/arm/boot/dts/sun8i-h3.dtsi|   5 +
 arch/arm/boot/dts/sunxi-h3-h5.dtsi |  36 ++
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c|   2 +-
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c  |  14 +-
 drivers/gpu/drm/sun4i/Kconfig  |   9 +
 drivers/gpu/drm/sun4i/Makefile |   1 +
 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c  | 500 +
 15 files changed, 950 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c

-- 
2.14.1

[RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI

2017-09-20 Thread Jernej Skrabec 
[added media mailing list due to CEC question]

This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only
video and CEC functionality is supported. Audio needs more tweaks.

Series is based on the H3 DE2 patch series available on mailing list:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/522697.html
(ignore patches marked with [NOT FOR REVIEW NOW] tag)

Patch 1 adds support for polling plug detection since custom PHY used here
doesn't support HPD interrupt.

Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits
same issues as HDMI controller used in iMX6 SoCs.

Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.

Patch 4 adds dt bindings documentation.

Patch 5 adds actual H3 HDMI glue driver.

Patch 6 and 7 add HDMI node to DT and enable it where needed.

Allwinner used DW HDMI controller in a non standard way:
- register offsets obfuscation layer, which can fortunately be turned off
- register read lock, which has to be disabled by magic number
- custom PHY, which have to be initialized before DW HDMI controller
- non standard clocks
- no HPD interrupt

Because of that, I have two questions:
- Since HPD have to be polled, is it enough just to enable poll mode? I'm
  mainly concerned about invalidating CEC address here.
- PHY has to be initialized before DW HDMI controller to disable offset
  obfuscation and read lock among other things. This means that all clocks have
  to be enabled in glue driver. This poses a problem, since when using
  component model, dw-hdmi bridge uses drvdata for it's own private data and
  prevents glue layer to pass a pointer to unbind function, where clocks should
  be disabled. I noticed same issue in meson DW HDMI glue driver, where clocks
  are also not disabled when unbind callback is called. I noticed that when H3
  SoC is shutdown, HDMI output is still enabled and lastest image is shown on
  monitor until it is unplugged from power supply. Is there any simple solution
  to this?

Chen-Yu,
TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I think
it is safe to assume that divider in HDMI clock doesn't have any effect.

Branch based on linux-next from 1. September with integrated patches is
available here:
https://github.com/jernejsk/linux-1/tree/h3_hdmi_rfc

Some additonal info about H3 HDMI:
https://linux-sunxi.org/DWC_HDMI_Controller

Thanks to Jens Kuske, who figured out that it is actually DW HDMI controller
and mapped scrambled register offsets to original ones.

Icenowy Zheng (1):
  ARM: sun8i: h3: Add DesignWare HDMI controller node

Jernej Skrabec (6):
  drm: bridge: Enable polling hpd event in dw_hdmi
  drm: bridge: Enable workaround in dw_hdmi for v1.32a
  clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
  dt-bindings: Document Allwinner DWC HDMI TX node
  drm: sun4i: Add a glue for the DesignWare HDMI controller in H3
  ARM: sun8i: h3: Enable HDMI output on H3 boards

 .../bindings/display/sunxi/sun4i-drm.txt   | 158 ++-
 arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts|  33 ++
 arch/arm/boot/dts/sun8i-h3-beelink-x2.dts  |  33 ++
 arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts   |  33 ++
 arch/arm/boot/dts/sun8i-h3-orangepi-2.dts  |  33 ++
 arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts   |  33 ++
 arch/arm/boot/dts/sun8i-h3-orangepi-one.dts|  33 ++
 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts |  33 ++
 arch/arm/boot/dts/sun8i-h3.dtsi|   5 +
 arch/arm/boot/dts/sunxi-h3-h5.dtsi |  36 ++
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c|   2 +-
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c  |  14 +-
 drivers/gpu/drm/sun4i/Kconfig  |   9 +
 drivers/gpu/drm/sun4i/Makefile |   1 +
 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c  | 500 +
 15 files changed, 950 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c

-- 
2.14.1