Re: [RFC PATCH 0/2] Introduce interface for default DMA pool
> On 2017. Jul 17., at 10:58, Vladimir Murzinwrote: > > Hi, > > This is follow-up for Christoph complain of overloading the current > dma coherent infrastructure with the global pool. To address that I > implemented Robin's idea of the new interface to the global pool and > wire up it with (only existent user) ARM NOMMU. Since I have not > heard from Vitaly and/or George of their use of global pool, I'm > leaving ARM MMU part to them. > > [1] https://lkml.org/lkml/2017/7/7/370 > I’ve tested the patches on Atmel SAMV7 SoC, and it works for me without any issues, so you can add my Tested-by. Thanks for the patches! Booting Linux on physical CPU 0x0 Linux version 4.13.0-rc1 (root@devel) (gcc version 4.9.2 ( 4.9.2-10)) #3 Wed Jul 19 04:48:18 EDT 2017 CPU: ARMv7-M [410fc271] revision 1 (ARMv7M), cr= CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache OF: fdt: Machine model: SAME70-sampione board ... Reserved memory: created DMA memory pool at 0x73e0, size 2 MiB OF: reserved mem: initialized node linux,dma, compatible id shared-dma-pool Using ARMv7 PMSA Compliant MPU. Region independence: No, Used 4 of 16 regions ... DMA: default coherent area is set ...
Re: [RFC PATCH 0/2] Introduce interface for default DMA pool
> On 2017. Jul 17., at 10:58, Vladimir Murzin wrote: > > Hi, > > This is follow-up for Christoph complain of overloading the current > dma coherent infrastructure with the global pool. To address that I > implemented Robin's idea of the new interface to the global pool and > wire up it with (only existent user) ARM NOMMU. Since I have not > heard from Vitaly and/or George of their use of global pool, I'm > leaving ARM MMU part to them. > > [1] https://lkml.org/lkml/2017/7/7/370 > I’ve tested the patches on Atmel SAMV7 SoC, and it works for me without any issues, so you can add my Tested-by. Thanks for the patches! Booting Linux on physical CPU 0x0 Linux version 4.13.0-rc1 (root@devel) (gcc version 4.9.2 ( 4.9.2-10)) #3 Wed Jul 19 04:48:18 EDT 2017 CPU: ARMv7-M [410fc271] revision 1 (ARMv7M), cr= CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache OF: fdt: Machine model: SAME70-sampione board ... Reserved memory: created DMA memory pool at 0x73e0, size 2 MiB OF: reserved mem: initialized node linux,dma, compatible id shared-dma-pool Using ARMv7 PMSA Compliant MPU. Region independence: No, Used 4 of 16 regions ... DMA: default coherent area is set ...
[RFC PATCH 0/2] Introduce interface for default DMA pool
Hi, This is follow-up for Christoph complain of overloading the current dma coherent infrastructure with the global pool. To address that I implemented Robin's idea of the new interface to the global pool and wire up it with (only existent user) ARM NOMMU. Since I have not heard from Vitaly and/or George of their use of global pool, I'm leaving ARM MMU part to them. [1] https://lkml.org/lkml/2017/7/7/370 Vladimir Murzin (2): drivers: dma-coherent: Introduce interface for default DMA pool ARM: NOMMU: Wire-up default DMA interface arch/arm/mm/dma-mapping-nommu.c | 45 +--- drivers/base/dma-coherent.c | 159 ++-- include/linux/dma-mapping.h | 24 ++ 3 files changed, 166 insertions(+), 62 deletions(-) -- 2.0.0
[RFC PATCH 0/2] Introduce interface for default DMA pool
Hi, This is follow-up for Christoph complain of overloading the current dma coherent infrastructure with the global pool. To address that I implemented Robin's idea of the new interface to the global pool and wire up it with (only existent user) ARM NOMMU. Since I have not heard from Vitaly and/or George of their use of global pool, I'm leaving ARM MMU part to them. [1] https://lkml.org/lkml/2017/7/7/370 Vladimir Murzin (2): drivers: dma-coherent: Introduce interface for default DMA pool ARM: NOMMU: Wire-up default DMA interface arch/arm/mm/dma-mapping-nommu.c | 45 +--- drivers/base/dma-coherent.c | 159 ++-- include/linux/dma-mapping.h | 24 ++ 3 files changed, 166 insertions(+), 62 deletions(-) -- 2.0.0