[PATCH v6 2/3] dmaengine: mediatek: Add MediaTek High-Speed DMA controller for MT7622 and MT7623 SoC

2018-03-07 Thread sean.wang 
From: Sean Wang 

MediaTek High-Speed DMA controller (HSDMA) on MT7622 and MT7623 SoC has
a single ring is dedicated to memory-to-memory transfer through ring based
descriptor management.

Even though there is only one physical ring available inside HSDMA, the
driver can be easily extended to the support of multiple virtual channels
processing simultaneously by means of DMA_VIRTUAL_CHANNELS effort.

Signed-off-by: Sean Wang 
Cc: Randy Dunlap 
Cc: Fengguang Wu 
Cc: Julia Lawall 
---
 drivers/dma/Kconfig  |2 +
 drivers/dma/Makefile |1 +
 drivers/dma/mediatek/Kconfig |   13 +
 drivers/dma/mediatek/Makefile|1 +
 drivers/dma/mediatek/mtk-hsdma.c | 1056 ++
 5 files changed, 1073 insertions(+)
 create mode 100644 drivers/dma/mediatek/Kconfig
 create mode 100644 drivers/dma/mediatek/Makefile
 create mode 100644 drivers/dma/mediatek/mtk-hsdma.c

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 27df3e2..86ace76 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -633,6 +633,8 @@ config ZX_DMA
 # driver files
 source "drivers/dma/bestcomm/Kconfig"
 
+source "drivers/dma/mediatek/Kconfig"
+
 source "drivers/dma/qcom/Kconfig"
 
 source "drivers/dma/dw/Kconfig"
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index b9dca8a..7a57b97 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -75,5 +75,6 @@ obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
 obj-$(CONFIG_ZX_DMA) += zx_dma.o
 obj-$(CONFIG_ST_FDMA) += st_fdma.o
 
+obj-y += mediatek/
 obj-y += qcom/
 obj-y += xilinx/
diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
new file mode 100644
index 000..27bac0b
--- /dev/null
+++ b/drivers/dma/mediatek/Kconfig
@@ -0,0 +1,13 @@
+
+config MTK_HSDMA
+   tristate "MediaTek High-Speed DMA controller support"
+   depends on ARCH_MEDIATEK || COMPILE_TEST
+   select DMA_ENGINE
+   select DMA_VIRTUAL_CHANNELS
+   ---help---
+ Enable support for High-Speed DMA controller on MediaTek
+ SoCs.
+
+ This controller provides the channels which is dedicated to
+ memory-to-memory transfer to offload from CPU through ring-
+ based descriptor management.
diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
new file mode 100644
index 000..6e778f8
--- /dev/null
+++ b/drivers/dma/mediatek/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
diff --git a/drivers/dma/mediatek/mtk-hsdma.c b/drivers/dma/mediatek/mtk-hsdma.c
new file mode 100644
index 000..b7ec56a
--- /dev/null
+++ b/drivers/dma/mediatek/mtk-hsdma.c
@@ -0,0 +1,1056 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017-2018 MediaTek Inc.
+
+/*
+ * Driver for MediaTek High-Speed DMA Controller
+ *
+ * Author: Sean Wang 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../virt-dma.h"
+
+#define MTK_HSDMA_USEC_POLL20
+#define MTK_HSDMA_TIMEOUT_POLL 20
+#define MTK_HSDMA_DMA_BUSWIDTHSBIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+
+/* The default number of virtual channel */
+#define MTK_HSDMA_NR_VCHANS3
+
+/* Only one physical channel supported */
+#define MTK_HSDMA_NR_MAX_PCHANS1
+
+/* Macro for physical descriptor (PD) manipulation */
+/* The number of PD which must be 2 of power */
+#define MTK_DMA_SIZE   64
+#define MTK_HSDMA_NEXT_DESP_IDX(x, y)  (((x) + 1) & ((y) - 1))
+#define MTK_HSDMA_LAST_DESP_IDX(x, y)  (((x) - 1) & ((y) - 1))
+#define MTK_HSDMA_MAX_LEN  0x3f80
+#define MTK_HSDMA_ALIGN_SIZE   4
+#define MTK_HSDMA_PLEN_MASK0x3fff
+#define MTK_HSDMA_DESC_PLEN(x) (((x) & MTK_HSDMA_PLEN_MASK) << 16)
+#define MTK_HSDMA_DESC_PLEN_GET(x) (((x) >> 16) & MTK_HSDMA_PLEN_MASK)
+
+/* Registers for underlying ring manipulation */
+#define MTK_HSDMA_TX_BASE  0x0
+#define MTK_HSDMA_TX_CNT   0x4
+#define MTK_HSDMA_TX_CPU   0x8
+#define MTK_HSDMA_TX_DMA   0xc
+#define MTK_HSDMA_RX_BASE  0x100
+#define MTK_HSDMA_RX_CNT   0x104
+#define MTK_HSDMA_RX_CPU   0x108
+#define MTK_HSDMA_RX_DMA   0x10c
+
+/* Registers for global setup */
+#define MTK_HSDMA_GLO  0x204
+#define MTK_HSDMA_GLO_MULTI_DMABIT(10)
+#define MTK_HSDMA_TX_WB_DDONE  BIT(6)
+#define MTK_HSDMA_BURST_64BYTES(0x2 << 4)
+#define MTK_HSDMA_GLO_RX_BUSY  BIT(3)
+#define MTK_HSDMA_GLO_RX_DMA   BIT(2)
+#define MTK_HSDMA_GLO_TX_BUSY  BIT(1)
+#define MTK_HSDMA_GLO_TX_DMA   BIT(0)
+#define MTK_HSDMA_GLO_DMA

[PATCH v6 2/3] dmaengine: mediatek: Add MediaTek High-Speed DMA controller for MT7622 and MT7623 SoC

2018-03-07 Thread sean.wang 
From: Sean Wang 

MediaTek High-Speed DMA controller (HSDMA) on MT7622 and MT7623 SoC has
a single ring is dedicated to memory-to-memory transfer through ring based
descriptor management.

Even though there is only one physical ring available inside HSDMA, the
driver can be easily extended to the support of multiple virtual channels
processing simultaneously by means of DMA_VIRTUAL_CHANNELS effort.

Signed-off-by: Sean Wang 
Cc: Randy Dunlap 
Cc: Fengguang Wu 
Cc: Julia Lawall 
---
 drivers/dma/Kconfig  |2 +
 drivers/dma/Makefile |1 +
 drivers/dma/mediatek/Kconfig |   13 +
 drivers/dma/mediatek/Makefile|1 +
 drivers/dma/mediatek/mtk-hsdma.c | 1056 ++
 5 files changed, 1073 insertions(+)
 create mode 100644 drivers/dma/mediatek/Kconfig
 create mode 100644 drivers/dma/mediatek/Makefile
 create mode 100644 drivers/dma/mediatek/mtk-hsdma.c

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 27df3e2..86ace76 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -633,6 +633,8 @@ config ZX_DMA
 # driver files
 source "drivers/dma/bestcomm/Kconfig"
 
+source "drivers/dma/mediatek/Kconfig"
+
 source "drivers/dma/qcom/Kconfig"
 
 source "drivers/dma/dw/Kconfig"
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index b9dca8a..7a57b97 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -75,5 +75,6 @@ obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
 obj-$(CONFIG_ZX_DMA) += zx_dma.o
 obj-$(CONFIG_ST_FDMA) += st_fdma.o
 
+obj-y += mediatek/
 obj-y += qcom/
 obj-y += xilinx/
diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
new file mode 100644
index 000..27bac0b
--- /dev/null
+++ b/drivers/dma/mediatek/Kconfig
@@ -0,0 +1,13 @@
+
+config MTK_HSDMA
+   tristate "MediaTek High-Speed DMA controller support"
+   depends on ARCH_MEDIATEK || COMPILE_TEST
+   select DMA_ENGINE
+   select DMA_VIRTUAL_CHANNELS
+   ---help---
+ Enable support for High-Speed DMA controller on MediaTek
+ SoCs.
+
+ This controller provides the channels which is dedicated to
+ memory-to-memory transfer to offload from CPU through ring-
+ based descriptor management.
diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
new file mode 100644
index 000..6e778f8
--- /dev/null
+++ b/drivers/dma/mediatek/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
diff --git a/drivers/dma/mediatek/mtk-hsdma.c b/drivers/dma/mediatek/mtk-hsdma.c
new file mode 100644
index 000..b7ec56a
--- /dev/null
+++ b/drivers/dma/mediatek/mtk-hsdma.c
@@ -0,0 +1,1056 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017-2018 MediaTek Inc.
+
+/*
+ * Driver for MediaTek High-Speed DMA Controller
+ *
+ * Author: Sean Wang 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../virt-dma.h"
+
+#define MTK_HSDMA_USEC_POLL20
+#define MTK_HSDMA_TIMEOUT_POLL 20
+#define MTK_HSDMA_DMA_BUSWIDTHSBIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+
+/* The default number of virtual channel */
+#define MTK_HSDMA_NR_VCHANS3
+
+/* Only one physical channel supported */
+#define MTK_HSDMA_NR_MAX_PCHANS1
+
+/* Macro for physical descriptor (PD) manipulation */
+/* The number of PD which must be 2 of power */
+#define MTK_DMA_SIZE   64
+#define MTK_HSDMA_NEXT_DESP_IDX(x, y)  (((x) + 1) & ((y) - 1))
+#define MTK_HSDMA_LAST_DESP_IDX(x, y)  (((x) - 1) & ((y) - 1))
+#define MTK_HSDMA_MAX_LEN  0x3f80
+#define MTK_HSDMA_ALIGN_SIZE   4
+#define MTK_HSDMA_PLEN_MASK0x3fff
+#define MTK_HSDMA_DESC_PLEN(x) (((x) & MTK_HSDMA_PLEN_MASK) << 16)
+#define MTK_HSDMA_DESC_PLEN_GET(x) (((x) >> 16) & MTK_HSDMA_PLEN_MASK)
+
+/* Registers for underlying ring manipulation */
+#define MTK_HSDMA_TX_BASE  0x0
+#define MTK_HSDMA_TX_CNT   0x4
+#define MTK_HSDMA_TX_CPU   0x8
+#define MTK_HSDMA_TX_DMA   0xc
+#define MTK_HSDMA_RX_BASE  0x100
+#define MTK_HSDMA_RX_CNT   0x104
+#define MTK_HSDMA_RX_CPU   0x108
+#define MTK_HSDMA_RX_DMA   0x10c
+
+/* Registers for global setup */
+#define MTK_HSDMA_GLO  0x204
+#define MTK_HSDMA_GLO_MULTI_DMABIT(10)
+#define MTK_HSDMA_TX_WB_DDONE  BIT(6)
+#define MTK_HSDMA_BURST_64BYTES(0x2 << 4)
+#define MTK_HSDMA_GLO_RX_BUSY  BIT(3)
+#define MTK_HSDMA_GLO_RX_DMA   BIT(2)
+#define MTK_HSDMA_GLO_TX_BUSY  BIT(1)
+#define MTK_HSDMA_GLO_TX_DMA   BIT(0)
+#define MTK_HSDMA_GLO_DMA  (MTK_HSDMA_GLO_TX_DMA | \
+MTK_HSDMA_GLO_RX_DMA)
+#define MTK_HSDMA_GLO_BUSY (MTK_HSDMA_GLO_RX_BUSY | \