On 16/03/2016 09:21, Suravee Suthikulpanit wrote:
>> Strictly speaking the address of the 0xFEE0 translation is
>> unnecessary and it could be all zeroes, but I suggest that you set up an
>> APIC access page like Intel does (4k only), using the special memslot.
>> The AVIC backing page can
On 16/03/2016 09:21, Suravee Suthikulpanit wrote:
>> Strictly speaking the address of the 0xFEE0 translation is
>> unnecessary and it could be all zeroes, but I suggest that you set up an
>> APIC access page like Intel does (4k only), using the special memslot.
>> The AVIC backing page can
Hi,
On 03/16/2016 02:20 PM, Paolo Bonzini wrote:
On 16/03/2016 07:22, Suravee Suthikulpanit wrote:
>This is mainly causing a large number of VMEXIT due to NPF.
Got it, it's here in the manual: "System software is responsible for
setting up a translation in the nested page table granting
Hi,
On 03/16/2016 02:20 PM, Paolo Bonzini wrote:
On 16/03/2016 07:22, Suravee Suthikulpanit wrote:
>This is mainly causing a large number of VMEXIT due to NPF.
Got it, it's here in the manual: "System software is responsible for
setting up a translation in the nested page table granting
On 16/03/2016 07:22, Suravee Suthikulpanit wrote:
> This is mainly causing a large number of VMEXIT due to NPF.
Got it, it's here in the manual: "System software is responsible for
setting up a translation in the nested page table granting guest read
and write permissions for accesses to the
On 16/03/2016 07:22, Suravee Suthikulpanit wrote:
> This is mainly causing a large number of VMEXIT due to NPF.
Got it, it's here in the manual: "System software is responsible for
setting up a translation in the nested page table granting guest read
and write permissions for accesses to the
Hi,
On 03/16/2016 12:22 AM, Paolo Bonzini wrote:
Why is this necessary? The APIC access page is a peculiarity of Intel
>>processors (and the special memslot for only needs to map 0xfee0 to
>>0xfee00fff; after that there is the MSI area).
>
>The current lapic regs page is allocated using
Hi,
On 03/16/2016 12:22 AM, Paolo Bonzini wrote:
Why is this necessary? The APIC access page is a peculiarity of Intel
>>processors (and the special memslot for only needs to map 0xfee0 to
>>0xfee00fff; after that there is the MSI area).
>
>The current lapic regs page is allocated using
On 15/03/2016 18:09, Suravee Suthikulpanit wrote:
> Hi
>
> On 03/07/2016 11:41 PM, Paolo Bonzini wrote:
>> On 04/03/2016 21:46, Suravee Suthikulpanit wrote:
>> > []
>>> +/* Note: This structure is per VM */
>>> +struct svm_vm_data {
>>> +atomic_t count;
>>> +u32 ldr_mode;
>>> +
On 15/03/2016 18:09, Suravee Suthikulpanit wrote:
> Hi
>
> On 03/07/2016 11:41 PM, Paolo Bonzini wrote:
>> On 04/03/2016 21:46, Suravee Suthikulpanit wrote:
>> > []
>>> +/* Note: This structure is per VM */
>>> +struct svm_vm_data {
>>> +atomic_t count;
>>> +u32 ldr_mode;
>>> +
Hi
On 03/07/2016 11:41 PM, Paolo Bonzini wrote:
On 04/03/2016 21:46, Suravee Suthikulpanit wrote:
> []
+/* Note: This structure is per VM */
+struct svm_vm_data {
+ atomic_t count;
+ u32 ldr_mode;
+ u32 avic_max_vcpu_id;
+ u32 avic_tag;
+
+ struct page
Hi
On 03/07/2016 11:41 PM, Paolo Bonzini wrote:
On 04/03/2016 21:46, Suravee Suthikulpanit wrote:
> []
+/* Note: This structure is per VM */
+struct svm_vm_data {
+ atomic_t count;
+ u32 ldr_mode;
+ u32 avic_max_vcpu_id;
+ u32 avic_tag;
+
+ struct page
On 04/03/2016 21:46, Suravee Suthikulpanit wrote:
> @@ -162,6 +170,37 @@ struct vcpu_svm {
>
> /* cached guest cpuid flags for faster access */
> bool nrips_enabled : 1;
> +
> + struct page *avic_bk_page;
> + void *in_kernel_lapic_regs;
> +};
> +
> +struct
On 04/03/2016 21:46, Suravee Suthikulpanit wrote:
> @@ -162,6 +170,37 @@ struct vcpu_svm {
>
> /* cached guest cpuid flags for faster access */
> bool nrips_enabled : 1;
> +
> + struct page *avic_bk_page;
> + void *in_kernel_lapic_regs;
> +};
> +
> +struct
This patch introduces AVIC-related data structure, and AVIC
initialization code.
There are three main data structures for AVIC:
* Virtual APIC (vAPIC) backing page (per-VCPU)
* Physical APIC ID table (per-VM)
* Logical APIC ID table (per-VM)
In order to accommodate the new per-VM
This patch introduces AVIC-related data structure, and AVIC
initialization code.
There are three main data structures for AVIC:
* Virtual APIC (vAPIC) backing page (per-VCPU)
* Physical APIC ID table (per-VM)
* Logical APIC ID table (per-VM)
In order to accommodate the new per-VM
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