> This is suboptimal though, as it will trigger a wbinvd() everytime
> when we hit a non present pte in a range, whether we did set the entry
> in question to not present or not.
Do you think that's common? I considered this while writing the code,
but figured it was just a oddball case not worth
On Mon, 11 Feb 2008, Andi Kleen wrote:
> The AMD64 pci-gart code sets pages not present to prevent
> cache coherency problems. When doing this it is safer to flush the
> caches too so that there are no cache lines left over from when
> the pages were still mapped.
>
> So consider clearing of t
The AMD64 pci-gart code sets pages not present to prevent
cache coherency problems. When doing this it is safer to flush the
caches too so that there are no cache lines left over from when
the pages were still mapped.
So consider clearing of the present bit as a cache flush indicator.
Note t
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