On Mon, Apr 16, 2018 at 02:46:40PM +0800, sxauwsk wrote:
> In case of xspi work in busy condition, may send bytes failed.
> once something wrong, spi controller did't work any more
>
> My test found this situation appear in both of read/write process.
> so when TX FIFO is full, add one byte delay
On Mon, Apr 16, 2018 at 02:46:40PM +0800, sxauwsk wrote:
> In case of xspi work in busy condition, may send bytes failed.
> once something wrong, spi controller did't work any more
>
> My test found this situation appear in both of read/write process.
> so when TX FIFO is full, add one byte delay
In case of xspi work in busy condition, may send bytes failed.
once something wrong, spi controller did't work any more
My test found this situation appear in both of read/write process.
so when TX FIFO is full, add one byte delay before send data;
Signed-off-by: sxauwsk
In case of xspi work in busy condition, may send bytes failed.
once something wrong, spi controller did't work any more
My test found this situation appear in both of read/write process.
so when TX FIFO is full, add one byte delay before send data;
Signed-off-by: sxauwsk
Signed-off-by: guojian
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