Re: [PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
On Thu, May 28, 2015 at 9:32 AM, Brian Norris
wrote:
> Hi Nga,
>
> Sorry for some delay here. This driver is mostly pretty good, and I
> think only a few very small tweaks are needed.
>
> (BTW, Rafal already made a few tiny comments, and I didn't see a follow
> up that fixes any of them.)
Thanks Brian for your reply. I will make the modification needed.
Because Rafal commented on this v3 and i want to wait for your
comments too, so that will be applied in coming v4.
>
> On Mon, Mar 16, 2015 at 01:16:22AM -0700, vn...@altera.com wrote:
>> From: VIET NGA DAO
>>
>> Altera Quad SPI Controller is a soft IP which enables access to Altera EPCQ
>> and
>> EPCS flash chips. This patch adds driver for these devices.
>>
>> Signed-off-by: VIET NGA DAO
>>
>> ---
>> v3:
>> - Change altera_epcq driver name to altera_quadspi for more generic name
>> - Implement flash name searching in altera_quadspi.c instead of spi-nor
>> - Edit the altra quadspi info table in spi-nor
>> - Remove wait_til_ready in all read,write, erase, lock, unlock functions
>> - Merge .h and .c into 1 file
>>
>> v2:
>> - Change to spi_nor structure
>> - Add lock and unlock functions for spi_nor
>> - Simplify the altera_epcq_lock function
>> - Replace reg by compatible in device tree
>> ---
>> .../devicetree/bindings/mtd/altera_quadspi.txt | 45 ++
>> drivers/mtd/spi-nor/Kconfig| 8 +
>> drivers/mtd/spi-nor/Makefile | 1 +
>> drivers/mtd/spi-nor/altera_quadspi.c | 608
>> +
>> drivers/mtd/spi-nor/spi-nor.c | 11 +
>> 5 files changed, 673 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mtd/altera_quadspi.txt
>> create mode 100644 drivers/mtd/spi-nor/altera_quadspi.c
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
>> b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
>> new file mode 100644
>> index 000..f5bdd35
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
>> @@ -0,0 +1,45 @@
>> +* MTD Altera QUADSPI driver
>> +
>> +Required properties:
>> +- compatible: Should be "altr,quadspi-1.0"
>> +- reg: Address and length of the register set for the device. It contains
>> + the information of registers in the same order as described by reg-names
>> +- reg-names: Should contain the reg names
>> + "csr_base": Should contain the register configuration base address
>> + "data_base": Should contain the data base address
>> +- is-epcs: boolean type.
>> + If present, the device contains EPCS flashes.
>> + Otherwise, it contains EPCQ flashes.
>
> Is this a property of the controller, or the flash? Seems like it should
> be in the subnode(s).
>
>> +- #address-cells: Must be <1>.
>> +- #size-cells: Must be <0>.
>> +- flash device tree subnode, there must be a node with the following fields:
>> + - compatible: Should contain the flash name
>
> You should list the names here.
>
>> + - #address-cells: please refer to /mtd/partition.txt
>> + - #size-cells: please refer to /mtd/partition.txt
>> + For partitions inside each flash, please refer to /mtd/partition.txt
>> +
>> +Example:
>> +
>> + quadspi_controller_0: quadspi@0x0 {
>> + compatible = "altr,quadspi-1.0";
>> + reg = <0x0001 0x 0x0020>,
>> + <0x 0x 0x0200>;
>> + reg-names = "csr_base", "data_base";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + flash0: epcq256@0 {
>> + compatible = "epcq256-nonjedec";
>
> I don't think the "-nonjedec" part is necessary; it's not really
> relevant to the binding, and it probably isn't even necessary for the ID
> table in spi-nor.c. Just stick with names like "altr,epcq256". But you
> probably should include the "altr," prefix. That will still work fine
> with the modalias stuff.
>
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + partition@0 {
>> + /* 16 MB for raw data. */
>> + label = "EPCQ Flash 0 raw
>> data";
>> + reg = <0x0 0x100>;
>> + };
>> + partition@100 {
>> + /* 16 MB for jffs2 data. */
>> + label = "EPCQ Flash 0 JFFS 2";
>> + reg = <0x100 0x100>;
>> + };
>> + };
>> + };
Re: [PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
Hi Nga,
Sorry for some delay here. This driver is mostly pretty good, and I
think only a few very small tweaks are needed.
(BTW, Rafal already made a few tiny comments, and I didn't see a follow
up that fixes any of them.)
On Mon, Mar 16, 2015 at 01:16:22AM -0700, vn...@altera.com wrote:
> From: VIET NGA DAO
>
> Altera Quad SPI Controller is a soft IP which enables access to Altera EPCQ
> and
> EPCS flash chips. This patch adds driver for these devices.
>
> Signed-off-by: VIET NGA DAO
>
> ---
> v3:
> - Change altera_epcq driver name to altera_quadspi for more generic name
> - Implement flash name searching in altera_quadspi.c instead of spi-nor
> - Edit the altra quadspi info table in spi-nor
> - Remove wait_til_ready in all read,write, erase, lock, unlock functions
> - Merge .h and .c into 1 file
>
> v2:
> - Change to spi_nor structure
> - Add lock and unlock functions for spi_nor
> - Simplify the altera_epcq_lock function
> - Replace reg by compatible in device tree
> ---
> .../devicetree/bindings/mtd/altera_quadspi.txt | 45 ++
> drivers/mtd/spi-nor/Kconfig| 8 +
> drivers/mtd/spi-nor/Makefile | 1 +
> drivers/mtd/spi-nor/altera_quadspi.c | 608
> +
> drivers/mtd/spi-nor/spi-nor.c | 11 +
> 5 files changed, 673 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/altera_quadspi.txt
> create mode 100644 drivers/mtd/spi-nor/altera_quadspi.c
>
> diff --git a/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
> b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
> new file mode 100644
> index 000..f5bdd35
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
> @@ -0,0 +1,45 @@
> +* MTD Altera QUADSPI driver
> +
> +Required properties:
> +- compatible: Should be "altr,quadspi-1.0"
> +- reg: Address and length of the register set for the device. It contains
> + the information of registers in the same order as described by reg-names
> +- reg-names: Should contain the reg names
> + "csr_base": Should contain the register configuration base address
> + "data_base": Should contain the data base address
> +- is-epcs: boolean type.
> + If present, the device contains EPCS flashes.
> + Otherwise, it contains EPCQ flashes.
Is this a property of the controller, or the flash? Seems like it should
be in the subnode(s).
> +- #address-cells: Must be <1>.
> +- #size-cells: Must be <0>.
> +- flash device tree subnode, there must be a node with the following fields:
> + - compatible: Should contain the flash name
You should list the names here.
> + - #address-cells: please refer to /mtd/partition.txt
> + - #size-cells: please refer to /mtd/partition.txt
> + For partitions inside each flash, please refer to /mtd/partition.txt
> +
> +Example:
> +
> + quadspi_controller_0: quadspi@0x0 {
> + compatible = "altr,quadspi-1.0";
> + reg = <0x0001 0x 0x0020>,
> + <0x 0x 0x0200>;
> + reg-names = "csr_base", "data_base";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + flash0: epcq256@0 {
> + compatible = "epcq256-nonjedec";
I don't think the "-nonjedec" part is necessary; it's not really
relevant to the binding, and it probably isn't even necessary for the ID
table in spi-nor.c. Just stick with names like "altr,epcq256". But you
probably should include the "altr," prefix. That will still work fine
with the modalias stuff.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + partition@0 {
> + /* 16 MB for raw data. */
> + label = "EPCQ Flash 0 raw data";
> + reg = <0x0 0x100>;
> + };
> + partition@100 {
> + /* 16 MB for jffs2 data. */
> + label = "EPCQ Flash 0 JFFS 2";
> + reg = <0x100 0x100>;
> + };
> + };
> + }; //end quadspi@0x0 (quadspi_controller_0)
> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
> index 64a4f0e..b9eed6d 100644
> --- a/drivers/mtd/spi-nor/Kconfig
> +++ b/drivers/mtd/spi-nor/Kconfig
> @@ -28,4 +28,12 @@ config SPI_FSL_QUADSPI
> This enables support for the Quad SPI controller in master mode.
>
Re: [PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
Hi Nga,
Sorry for some delay here. This driver is mostly pretty good, and I
think only a few very small tweaks are needed.
(BTW, Rafal already made a few tiny comments, and I didn't see a follow
up that fixes any of them.)
On Mon, Mar 16, 2015 at 01:16:22AM -0700, vn...@altera.com wrote:
From: VIET NGA DAO vn...@altera.com
Altera Quad SPI Controller is a soft IP which enables access to Altera EPCQ
and
EPCS flash chips. This patch adds driver for these devices.
Signed-off-by: VIET NGA DAO vn...@altera.com
---
v3:
- Change altera_epcq driver name to altera_quadspi for more generic name
- Implement flash name searching in altera_quadspi.c instead of spi-nor
- Edit the altra quadspi info table in spi-nor
- Remove wait_til_ready in all read,write, erase, lock, unlock functions
- Merge .h and .c into 1 file
v2:
- Change to spi_nor structure
- Add lock and unlock functions for spi_nor
- Simplify the altera_epcq_lock function
- Replace reg by compatible in device tree
---
.../devicetree/bindings/mtd/altera_quadspi.txt | 45 ++
drivers/mtd/spi-nor/Kconfig| 8 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/altera_quadspi.c | 608
+
drivers/mtd/spi-nor/spi-nor.c | 11 +
5 files changed, 673 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/altera_quadspi.txt
create mode 100644 drivers/mtd/spi-nor/altera_quadspi.c
diff --git a/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
new file mode 100644
index 000..f5bdd35
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
@@ -0,0 +1,45 @@
+* MTD Altera QUADSPI driver
+
+Required properties:
+- compatible: Should be altr,quadspi-1.0
+- reg: Address and length of the register set for the device. It contains
+ the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+ csr_base: Should contain the register configuration base address
+ data_base: Should contain the data base address
+- is-epcs: boolean type.
+ If present, the device contains EPCS flashes.
+ Otherwise, it contains EPCQ flashes.
Is this a property of the controller, or the flash? Seems like it should
be in the subnode(s).
+- #address-cells: Must be 1.
+- #size-cells: Must be 0.
+- flash device tree subnode, there must be a node with the following fields:
+ - compatible: Should contain the flash name
You should list the names here.
+ - #address-cells: please refer to /mtd/partition.txt
+ - #size-cells: please refer to /mtd/partition.txt
+ For partitions inside each flash, please refer to /mtd/partition.txt
+
+Example:
+
+ quadspi_controller_0: quadspi@0x0 {
+ compatible = altr,quadspi-1.0;
+ reg = 0x0001 0x 0x0020,
+ 0x 0x 0x0200;
+ reg-names = csr_base, data_base;
+ #address-cells = 1;
+ #size-cells = 0;
+ flash0: epcq256@0 {
+ compatible = epcq256-nonjedec;
I don't think the -nonjedec part is necessary; it's not really
relevant to the binding, and it probably isn't even necessary for the ID
table in spi-nor.c. Just stick with names like altr,epcq256. But you
probably should include the altr, prefix. That will still work fine
with the modalias stuff.
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0 {
+ /* 16 MB for raw data. */
+ label = EPCQ Flash 0 raw data;
+ reg = 0x0 0x100;
+ };
+ partition@100 {
+ /* 16 MB for jffs2 data. */
+ label = EPCQ Flash 0 JFFS 2;
+ reg = 0x100 0x100;
+ };
+ };
+ }; //end quadspi@0x0 (quadspi_controller_0)
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 64a4f0e..b9eed6d 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -28,4 +28,12 @@ config SPI_FSL_QUADSPI
This enables support for the Quad SPI controller in master mode.
We only connect the NOR to this controller now.
+config SPI_ALTERA_QUADSPI
+ tristate Support
Re: [PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
On Thu, May 28, 2015 at 9:32 AM, Brian Norris
computersforpe...@gmail.com wrote:
Hi Nga,
Sorry for some delay here. This driver is mostly pretty good, and I
think only a few very small tweaks are needed.
(BTW, Rafal already made a few tiny comments, and I didn't see a follow
up that fixes any of them.)
Thanks Brian for your reply. I will make the modification needed.
Because Rafal commented on this v3 and i want to wait for your
comments too, so that will be applied in coming v4.
On Mon, Mar 16, 2015 at 01:16:22AM -0700, vn...@altera.com wrote:
From: VIET NGA DAO vn...@altera.com
Altera Quad SPI Controller is a soft IP which enables access to Altera EPCQ
and
EPCS flash chips. This patch adds driver for these devices.
Signed-off-by: VIET NGA DAO vn...@altera.com
---
v3:
- Change altera_epcq driver name to altera_quadspi for more generic name
- Implement flash name searching in altera_quadspi.c instead of spi-nor
- Edit the altra quadspi info table in spi-nor
- Remove wait_til_ready in all read,write, erase, lock, unlock functions
- Merge .h and .c into 1 file
v2:
- Change to spi_nor structure
- Add lock and unlock functions for spi_nor
- Simplify the altera_epcq_lock function
- Replace reg by compatible in device tree
---
.../devicetree/bindings/mtd/altera_quadspi.txt | 45 ++
drivers/mtd/spi-nor/Kconfig| 8 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/altera_quadspi.c | 608
+
drivers/mtd/spi-nor/spi-nor.c | 11 +
5 files changed, 673 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/altera_quadspi.txt
create mode 100644 drivers/mtd/spi-nor/altera_quadspi.c
diff --git a/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
new file mode 100644
index 000..f5bdd35
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
@@ -0,0 +1,45 @@
+* MTD Altera QUADSPI driver
+
+Required properties:
+- compatible: Should be altr,quadspi-1.0
+- reg: Address and length of the register set for the device. It contains
+ the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+ csr_base: Should contain the register configuration base address
+ data_base: Should contain the data base address
+- is-epcs: boolean type.
+ If present, the device contains EPCS flashes.
+ Otherwise, it contains EPCQ flashes.
Is this a property of the controller, or the flash? Seems like it should
be in the subnode(s).
+- #address-cells: Must be 1.
+- #size-cells: Must be 0.
+- flash device tree subnode, there must be a node with the following fields:
+ - compatible: Should contain the flash name
You should list the names here.
+ - #address-cells: please refer to /mtd/partition.txt
+ - #size-cells: please refer to /mtd/partition.txt
+ For partitions inside each flash, please refer to /mtd/partition.txt
+
+Example:
+
+ quadspi_controller_0: quadspi@0x0 {
+ compatible = altr,quadspi-1.0;
+ reg = 0x0001 0x 0x0020,
+ 0x 0x 0x0200;
+ reg-names = csr_base, data_base;
+ #address-cells = 1;
+ #size-cells = 0;
+ flash0: epcq256@0 {
+ compatible = epcq256-nonjedec;
I don't think the -nonjedec part is necessary; it's not really
relevant to the binding, and it probably isn't even necessary for the ID
table in spi-nor.c. Just stick with names like altr,epcq256. But you
probably should include the altr, prefix. That will still work fine
with the modalias stuff.
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0 {
+ /* 16 MB for raw data. */
+ label = EPCQ Flash 0 raw
data;
+ reg = 0x0 0x100;
+ };
+ partition@100 {
+ /* 16 MB for jffs2 data. */
+ label = EPCQ Flash 0 JFFS 2;
+ reg = 0x100 0x100;
+ };
+ };
+ }; //end quadspi@0x0 (quadspi_controller_0)
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 64a4f0e..b9eed6d 100644
---
Re: [PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
Hi,
It has been long time since this patch was up. Could you please help
me to review?
Thanks,
Viet Nga
On Thu, Apr 23, 2015 at 2:39 PM, Nga Chi wrote:
> Hi Brian,
> Could you please spend some time help me to review this patch? It has
> been more than 1 month and i really hope can get this patch upstream
> by end of this month.
> Thanks,
> Viet Nga
>
> On Mon, Mar 16, 2015 at 4:16 PM, wrote:
>> From: VIET NGA DAO
>>
>> Altera Quad SPI Controller is a soft IP which enables access to Altera EPCQ
>> and
>> EPCS flash chips. This patch adds driver for these devices.
>>
>> Signed-off-by: VIET NGA DAO
>>
>> ---
>> v3:
>> - Change altera_epcq driver name to altera_quadspi for more generic name
>> - Implement flash name searching in altera_quadspi.c instead of spi-nor
>> - Edit the altra quadspi info table in spi-nor
>> - Remove wait_til_ready in all read,write, erase, lock, unlock functions
>> - Merge .h and .c into 1 file
>>
>> v2:
>> - Change to spi_nor structure
>> - Add lock and unlock functions for spi_nor
>> - Simplify the altera_epcq_lock function
>> - Replace reg by compatible in device tree
>> ---
>> .../devicetree/bindings/mtd/altera_quadspi.txt | 45 ++
>> drivers/mtd/spi-nor/Kconfig| 8 +
>> drivers/mtd/spi-nor/Makefile | 1 +
>> drivers/mtd/spi-nor/altera_quadspi.c | 608
>> +
>> drivers/mtd/spi-nor/spi-nor.c | 11 +
>> 5 files changed, 673 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mtd/altera_quadspi.txt
>> create mode 100644 drivers/mtd/spi-nor/altera_quadspi.c
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
>> b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
>> new file mode 100644
>> index 000..f5bdd35
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
>> @@ -0,0 +1,45 @@
>> +* MTD Altera QUADSPI driver
>> +
>> +Required properties:
>> +- compatible: Should be "altr,quadspi-1.0"
>> +- reg: Address and length of the register set for the device. It contains
>> + the information of registers in the same order as described by reg-names
>> +- reg-names: Should contain the reg names
>> + "csr_base": Should contain the register configuration base address
>> + "data_base": Should contain the data base address
>> +- is-epcs: boolean type.
>> + If present, the device contains EPCS flashes.
>> + Otherwise, it contains EPCQ flashes.
>> +- #address-cells: Must be <1>.
>> +- #size-cells: Must be <0>.
>> +- flash device tree subnode, there must be a node with the following fields:
>> + - compatible: Should contain the flash name
>> + - #address-cells: please refer to /mtd/partition.txt
>> + - #size-cells: please refer to /mtd/partition.txt
>> + For partitions inside each flash, please refer to /mtd/partition.txt
>> +
>> +Example:
>> +
>> + quadspi_controller_0: quadspi@0x0 {
>> + compatible = "altr,quadspi-1.0";
>> + reg = <0x0001 0x 0x0020>,
>> + <0x 0x 0x0200>;
>> + reg-names = "csr_base", "data_base";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + flash0: epcq256@0 {
>> + compatible = "epcq256-nonjedec";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + partition@0 {
>> + /* 16 MB for raw data. */
>> + label = "EPCQ Flash 0 raw
>> data";
>> + reg = <0x0 0x100>;
>> + };
>> + partition@100 {
>> + /* 16 MB for jffs2 data. */
>> + label = "EPCQ Flash 0 JFFS
>> 2";
>> + reg = <0x100 0x100>;
>> + };
>> + };
>> + }; //end quadspi@0x0 (quadspi_controller_0)
>> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
>> index 64a4f0e..b9eed6d 100644
>> --- a/drivers/mtd/spi-nor/Kconfig
>> +++ b/drivers/mtd/spi-nor/Kconfig
>> @@ -28,4 +28,12 @@ config SPI_FSL_QUADSPI
>> This enables support for the Quad SPI controller in master mode.
>> We only connect the NOR to this controller now.
>>
>> +config SPI_ALTERA_QUADSPI
>> + tristate "Support Altera EPCQ/EPCS Flash chips"
>> + depends on OF
>> +
Re: [PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
Hi,
It has been long time since this patch was up. Could you please help
me to review?
Thanks,
Viet Nga
On Thu, Apr 23, 2015 at 2:39 PM, Nga Chi ngach...@gmail.com wrote:
Hi Brian,
Could you please spend some time help me to review this patch? It has
been more than 1 month and i really hope can get this patch upstream
by end of this month.
Thanks,
Viet Nga
On Mon, Mar 16, 2015 at 4:16 PM, vn...@altera.com wrote:
From: VIET NGA DAO vn...@altera.com
Altera Quad SPI Controller is a soft IP which enables access to Altera EPCQ
and
EPCS flash chips. This patch adds driver for these devices.
Signed-off-by: VIET NGA DAO vn...@altera.com
---
v3:
- Change altera_epcq driver name to altera_quadspi for more generic name
- Implement flash name searching in altera_quadspi.c instead of spi-nor
- Edit the altra quadspi info table in spi-nor
- Remove wait_til_ready in all read,write, erase, lock, unlock functions
- Merge .h and .c into 1 file
v2:
- Change to spi_nor structure
- Add lock and unlock functions for spi_nor
- Simplify the altera_epcq_lock function
- Replace reg by compatible in device tree
---
.../devicetree/bindings/mtd/altera_quadspi.txt | 45 ++
drivers/mtd/spi-nor/Kconfig| 8 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/altera_quadspi.c | 608
+
drivers/mtd/spi-nor/spi-nor.c | 11 +
5 files changed, 673 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/altera_quadspi.txt
create mode 100644 drivers/mtd/spi-nor/altera_quadspi.c
diff --git a/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
new file mode 100644
index 000..f5bdd35
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
@@ -0,0 +1,45 @@
+* MTD Altera QUADSPI driver
+
+Required properties:
+- compatible: Should be altr,quadspi-1.0
+- reg: Address and length of the register set for the device. It contains
+ the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+ csr_base: Should contain the register configuration base address
+ data_base: Should contain the data base address
+- is-epcs: boolean type.
+ If present, the device contains EPCS flashes.
+ Otherwise, it contains EPCQ flashes.
+- #address-cells: Must be 1.
+- #size-cells: Must be 0.
+- flash device tree subnode, there must be a node with the following fields:
+ - compatible: Should contain the flash name
+ - #address-cells: please refer to /mtd/partition.txt
+ - #size-cells: please refer to /mtd/partition.txt
+ For partitions inside each flash, please refer to /mtd/partition.txt
+
+Example:
+
+ quadspi_controller_0: quadspi@0x0 {
+ compatible = altr,quadspi-1.0;
+ reg = 0x0001 0x 0x0020,
+ 0x 0x 0x0200;
+ reg-names = csr_base, data_base;
+ #address-cells = 1;
+ #size-cells = 0;
+ flash0: epcq256@0 {
+ compatible = epcq256-nonjedec;
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0 {
+ /* 16 MB for raw data. */
+ label = EPCQ Flash 0 raw
data;
+ reg = 0x0 0x100;
+ };
+ partition@100 {
+ /* 16 MB for jffs2 data. */
+ label = EPCQ Flash 0 JFFS
2;
+ reg = 0x100 0x100;
+ };
+ };
+ }; //end quadspi@0x0 (quadspi_controller_0)
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 64a4f0e..b9eed6d 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -28,4 +28,12 @@ config SPI_FSL_QUADSPI
This enables support for the Quad SPI controller in master mode.
We only connect the NOR to this controller now.
+config SPI_ALTERA_QUADSPI
+ tristate Support Altera EPCQ/EPCS Flash chips
+ depends on OF
+ help
+ This enables access to Altera EPCQ/EPCS flash chips, used for data
+ storage. See the driver source for the current list,
+ or to add other
Re: [PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
Hi Brian,
Could you please spend some time help me to review this patch? It has
been more than 1 month and i really hope can get this patch upstream
by end of this month.
Thanks,
Viet Nga
On Mon, Mar 16, 2015 at 4:16 PM, wrote:
> From: VIET NGA DAO
>
> Altera Quad SPI Controller is a soft IP which enables access to Altera EPCQ
> and
> EPCS flash chips. This patch adds driver for these devices.
>
> Signed-off-by: VIET NGA DAO
>
> ---
> v3:
> - Change altera_epcq driver name to altera_quadspi for more generic name
> - Implement flash name searching in altera_quadspi.c instead of spi-nor
> - Edit the altra quadspi info table in spi-nor
> - Remove wait_til_ready in all read,write, erase, lock, unlock functions
> - Merge .h and .c into 1 file
>
> v2:
> - Change to spi_nor structure
> - Add lock and unlock functions for spi_nor
> - Simplify the altera_epcq_lock function
> - Replace reg by compatible in device tree
> ---
> .../devicetree/bindings/mtd/altera_quadspi.txt | 45 ++
> drivers/mtd/spi-nor/Kconfig| 8 +
> drivers/mtd/spi-nor/Makefile | 1 +
> drivers/mtd/spi-nor/altera_quadspi.c | 608
> +
> drivers/mtd/spi-nor/spi-nor.c | 11 +
> 5 files changed, 673 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/altera_quadspi.txt
> create mode 100644 drivers/mtd/spi-nor/altera_quadspi.c
>
> diff --git a/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
> b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
> new file mode 100644
> index 000..f5bdd35
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
> @@ -0,0 +1,45 @@
> +* MTD Altera QUADSPI driver
> +
> +Required properties:
> +- compatible: Should be "altr,quadspi-1.0"
> +- reg: Address and length of the register set for the device. It contains
> + the information of registers in the same order as described by reg-names
> +- reg-names: Should contain the reg names
> + "csr_base": Should contain the register configuration base address
> + "data_base": Should contain the data base address
> +- is-epcs: boolean type.
> + If present, the device contains EPCS flashes.
> + Otherwise, it contains EPCQ flashes.
> +- #address-cells: Must be <1>.
> +- #size-cells: Must be <0>.
> +- flash device tree subnode, there must be a node with the following fields:
> + - compatible: Should contain the flash name
> + - #address-cells: please refer to /mtd/partition.txt
> + - #size-cells: please refer to /mtd/partition.txt
> + For partitions inside each flash, please refer to /mtd/partition.txt
> +
> +Example:
> +
> + quadspi_controller_0: quadspi@0x0 {
> + compatible = "altr,quadspi-1.0";
> + reg = <0x0001 0x 0x0020>,
> + <0x 0x 0x0200>;
> + reg-names = "csr_base", "data_base";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + flash0: epcq256@0 {
> + compatible = "epcq256-nonjedec";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + partition@0 {
> + /* 16 MB for raw data. */
> + label = "EPCQ Flash 0 raw
> data";
> + reg = <0x0 0x100>;
> + };
> + partition@100 {
> + /* 16 MB for jffs2 data. */
> + label = "EPCQ Flash 0 JFFS 2";
> + reg = <0x100 0x100>;
> + };
> + };
> + }; //end quadspi@0x0 (quadspi_controller_0)
> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
> index 64a4f0e..b9eed6d 100644
> --- a/drivers/mtd/spi-nor/Kconfig
> +++ b/drivers/mtd/spi-nor/Kconfig
> @@ -28,4 +28,12 @@ config SPI_FSL_QUADSPI
> This enables support for the Quad SPI controller in master mode.
> We only connect the NOR to this controller now.
>
> +config SPI_ALTERA_QUADSPI
> + tristate "Support Altera EPCQ/EPCS Flash chips"
> + depends on OF
> + help
> + This enables access to Altera EPCQ/EPCS flash chips, used for data
> + storage. See the driver source for the current list,
> + or to add other chips.
> +
> endif # MTD_SPI_NOR
> diff --git a/drivers/mtd/spi-nor/Makefile
Re: [PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
Hi Brian,
Could you please spend some time help me to review this patch? It has
been more than 1 month and i really hope can get this patch upstream
by end of this month.
Thanks,
Viet Nga
On Mon, Mar 16, 2015 at 4:16 PM, vn...@altera.com wrote:
From: VIET NGA DAO vn...@altera.com
Altera Quad SPI Controller is a soft IP which enables access to Altera EPCQ
and
EPCS flash chips. This patch adds driver for these devices.
Signed-off-by: VIET NGA DAO vn...@altera.com
---
v3:
- Change altera_epcq driver name to altera_quadspi for more generic name
- Implement flash name searching in altera_quadspi.c instead of spi-nor
- Edit the altra quadspi info table in spi-nor
- Remove wait_til_ready in all read,write, erase, lock, unlock functions
- Merge .h and .c into 1 file
v2:
- Change to spi_nor structure
- Add lock and unlock functions for spi_nor
- Simplify the altera_epcq_lock function
- Replace reg by compatible in device tree
---
.../devicetree/bindings/mtd/altera_quadspi.txt | 45 ++
drivers/mtd/spi-nor/Kconfig| 8 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/altera_quadspi.c | 608
+
drivers/mtd/spi-nor/spi-nor.c | 11 +
5 files changed, 673 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/altera_quadspi.txt
create mode 100644 drivers/mtd/spi-nor/altera_quadspi.c
diff --git a/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
new file mode 100644
index 000..f5bdd35
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
@@ -0,0 +1,45 @@
+* MTD Altera QUADSPI driver
+
+Required properties:
+- compatible: Should be altr,quadspi-1.0
+- reg: Address and length of the register set for the device. It contains
+ the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+ csr_base: Should contain the register configuration base address
+ data_base: Should contain the data base address
+- is-epcs: boolean type.
+ If present, the device contains EPCS flashes.
+ Otherwise, it contains EPCQ flashes.
+- #address-cells: Must be 1.
+- #size-cells: Must be 0.
+- flash device tree subnode, there must be a node with the following fields:
+ - compatible: Should contain the flash name
+ - #address-cells: please refer to /mtd/partition.txt
+ - #size-cells: please refer to /mtd/partition.txt
+ For partitions inside each flash, please refer to /mtd/partition.txt
+
+Example:
+
+ quadspi_controller_0: quadspi@0x0 {
+ compatible = altr,quadspi-1.0;
+ reg = 0x0001 0x 0x0020,
+ 0x 0x 0x0200;
+ reg-names = csr_base, data_base;
+ #address-cells = 1;
+ #size-cells = 0;
+ flash0: epcq256@0 {
+ compatible = epcq256-nonjedec;
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0 {
+ /* 16 MB for raw data. */
+ label = EPCQ Flash 0 raw
data;
+ reg = 0x0 0x100;
+ };
+ partition@100 {
+ /* 16 MB for jffs2 data. */
+ label = EPCQ Flash 0 JFFS 2;
+ reg = 0x100 0x100;
+ };
+ };
+ }; //end quadspi@0x0 (quadspi_controller_0)
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 64a4f0e..b9eed6d 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -28,4 +28,12 @@ config SPI_FSL_QUADSPI
This enables support for the Quad SPI controller in master mode.
We only connect the NOR to this controller now.
+config SPI_ALTERA_QUADSPI
+ tristate Support Altera EPCQ/EPCS Flash chips
+ depends on OF
+ help
+ This enables access to Altera EPCQ/EPCS flash chips, used for data
+ storage. See the driver source for the current list,
+ or to add other chips.
+
endif # MTD_SPI_NOR
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index 6a7ce14..1a36a72 100644
--- a/drivers/mtd/spi-nor/Makefile
+++
Re: [PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
Hi,
Could you please help me to review this patch?
Thanks
On Mon, Mar 16, 2015 at 4:40 PM, Viet Nga Dao wrote:
> On Mon, Mar 16, 2015 at 4:35 PM, Rafał Miłecki wrote:
>> On 16 March 2015 at 09:16, wrote:
>>> +static struct flash_device flash_devices[] = {
>>> + FLASH_ID("epcq16-nonjedec", 2, 0x15),
>>> + FLASH_ID("epcq32-nonjedec", 2, 0x16),
>>> + FLASH_ID("epcq64-nonjedec", 2, 0x17),
>>> + FLASH_ID("epcq128-nonjedec", 2, 0x18),
>>> + FLASH_ID("epcq256-nonjedec", 2, 0x19),
>>> + FLASH_ID("epcq512-nonjedec", 2, 0x20),
>>
>> You could probably use EPCQ_OPCODE_ID
>>
>>
>>> +
>>> + FLASH_ID("epcs16-nonjedec", 1, 0x14),
>>> + FLASH_ID("epcs64-nonjedec", 1, 0x16),
>>> + FLASH_ID("epcs128-nonjedec", 1, 0x18),
>>
>> And EPCS_OPCODE_ID here.
>>
> Noted
>>
>>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
>>> index 43bb552..ad0c274 100644
>>> --- a/drivers/mtd/spi-nor/spi-nor.c
>>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>>> @@ -683,6 +683,17 @@ static const struct spi_device_id spi_nor_ids[] = {
>>> { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE |
>>> SPI_NOR_NO_FR) },
>>> { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE |
>>> SPI_NOR_NO_FR) },
>>> { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE |
>>> SPI_NOR_NO_FR) },
>>> +
>>> + /* Altera EPCQ/EPCS Flashes */
>>> + { "epcq16-nonjedec", INFO(0, 0, 0x1, 32, 0) },
>>> + { "epcq32-nonjedec", INFO(0, 0, 0x1, 64, 0) },
>>> + { "epcq64-nonjedec", INFO(0, 0, 0x1, 128, 0) },
>>> + { "epcq128-nonjedec", INFO(0, 0, 0x1, 256, 0) },
>>> + { "epcq256-nonjedec", INFO(0, 0, 0x1, 512, 0) },
>>> + { "epcq512-nonjedec", INFO(0, 0, 0x1, 1024, 0) },
>>> + { "epcs16-nonjedec", INFO(0, 0, 0x1, 32, 0) },
>>> + { "epcs64-nonjedec", INFO(0, 0, 0x1, 128, 0) },
>>> + { "epcs128-nonjedec", INFO(0, 0, 0x4, 256, 0) },
>>> { },
>>> };
>>
>> But mostly, I just wanted to say I like your integration with spi-nor.
>> Nice work :)
>>
>> --
>> Rafał
>
> Thank you. This is all thanks to you and Brian for helpful comments. I
> learned a lot :)
--
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
Hi,
Could you please help me to review this patch?
Thanks
On Mon, Mar 16, 2015 at 4:40 PM, Viet Nga Dao vn...@altera.com wrote:
On Mon, Mar 16, 2015 at 4:35 PM, Rafał Miłecki zaj...@gmail.com wrote:
On 16 March 2015 at 09:16, vn...@altera.com wrote:
+static struct flash_device flash_devices[] = {
+ FLASH_ID(epcq16-nonjedec, 2, 0x15),
+ FLASH_ID(epcq32-nonjedec, 2, 0x16),
+ FLASH_ID(epcq64-nonjedec, 2, 0x17),
+ FLASH_ID(epcq128-nonjedec, 2, 0x18),
+ FLASH_ID(epcq256-nonjedec, 2, 0x19),
+ FLASH_ID(epcq512-nonjedec, 2, 0x20),
You could probably use EPCQ_OPCODE_ID
+
+ FLASH_ID(epcs16-nonjedec, 1, 0x14),
+ FLASH_ID(epcs64-nonjedec, 1, 0x16),
+ FLASH_ID(epcs128-nonjedec, 1, 0x18),
And EPCS_OPCODE_ID here.
Noted
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 43bb552..ad0c274 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -683,6 +683,17 @@ static const struct spi_device_id spi_nor_ids[] = {
{ cat25c09, CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE |
SPI_NOR_NO_FR) },
{ cat25c17, CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE |
SPI_NOR_NO_FR) },
{ cat25128, CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE |
SPI_NOR_NO_FR) },
+
+ /* Altera EPCQ/EPCS Flashes */
+ { epcq16-nonjedec, INFO(0, 0, 0x1, 32, 0) },
+ { epcq32-nonjedec, INFO(0, 0, 0x1, 64, 0) },
+ { epcq64-nonjedec, INFO(0, 0, 0x1, 128, 0) },
+ { epcq128-nonjedec, INFO(0, 0, 0x1, 256, 0) },
+ { epcq256-nonjedec, INFO(0, 0, 0x1, 512, 0) },
+ { epcq512-nonjedec, INFO(0, 0, 0x1, 1024, 0) },
+ { epcs16-nonjedec, INFO(0, 0, 0x1, 32, 0) },
+ { epcs64-nonjedec, INFO(0, 0, 0x1, 128, 0) },
+ { epcs128-nonjedec, INFO(0, 0, 0x4, 256, 0) },
{ },
};
But mostly, I just wanted to say I like your integration with spi-nor.
Nice work :)
--
Rafał
Thank you. This is all thanks to you and Brian for helpful comments. I
learned a lot :)
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
Hi Brian,
Can you help me to review this patch of mine?
Thanks,
Nga
On Mon, Mar 16, 2015 at 4:16 PM, wrote:
> From: VIET NGA DAO
>
> Altera Quad SPI Controller is a soft IP which enables access to Altera EPCQ
> and
> EPCS flash chips. This patch adds driver for these devices.
>
> Signed-off-by: VIET NGA DAO
>
> ---
> v3:
> - Change altera_epcq driver name to altera_quadspi for more generic name
> - Implement flash name searching in altera_quadspi.c instead of spi-nor
> - Edit the altra quadspi info table in spi-nor
> - Remove wait_til_ready in all read,write, erase, lock, unlock functions
> - Merge .h and .c into 1 file
>
> v2:
> - Change to spi_nor structure
> - Add lock and unlock functions for spi_nor
> - Simplify the altera_epcq_lock function
> - Replace reg by compatible in device tree
> ---
> .../devicetree/bindings/mtd/altera_quadspi.txt | 45 ++
> drivers/mtd/spi-nor/Kconfig| 8 +
> drivers/mtd/spi-nor/Makefile | 1 +
> drivers/mtd/spi-nor/altera_quadspi.c | 608
> +
> drivers/mtd/spi-nor/spi-nor.c | 11 +
> 5 files changed, 673 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/altera_quadspi.txt
> create mode 100644 drivers/mtd/spi-nor/altera_quadspi.c
>
> diff --git a/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
> b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
> new file mode 100644
> index 000..f5bdd35
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
> @@ -0,0 +1,45 @@
> +* MTD Altera QUADSPI driver
> +
> +Required properties:
> +- compatible: Should be "altr,quadspi-1.0"
> +- reg: Address and length of the register set for the device. It contains
> + the information of registers in the same order as described by reg-names
> +- reg-names: Should contain the reg names
> + "csr_base": Should contain the register configuration base address
> + "data_base": Should contain the data base address
> +- is-epcs: boolean type.
> + If present, the device contains EPCS flashes.
> + Otherwise, it contains EPCQ flashes.
> +- #address-cells: Must be <1>.
> +- #size-cells: Must be <0>.
> +- flash device tree subnode, there must be a node with the following fields:
> + - compatible: Should contain the flash name
> + - #address-cells: please refer to /mtd/partition.txt
> + - #size-cells: please refer to /mtd/partition.txt
> + For partitions inside each flash, please refer to /mtd/partition.txt
> +
> +Example:
> +
> + quadspi_controller_0: quadspi@0x0 {
> + compatible = "altr,quadspi-1.0";
> + reg = <0x0001 0x 0x0020>,
> + <0x 0x 0x0200>;
> + reg-names = "csr_base", "data_base";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + flash0: epcq256@0 {
> + compatible = "epcq256-nonjedec";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + partition@0 {
> + /* 16 MB for raw data. */
> + label = "EPCQ Flash 0 raw
> data";
> + reg = <0x0 0x100>;
> + };
> + partition@100 {
> + /* 16 MB for jffs2 data. */
> + label = "EPCQ Flash 0 JFFS 2";
> + reg = <0x100 0x100>;
> + };
> + };
> + }; //end quadspi@0x0 (quadspi_controller_0)
> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
> index 64a4f0e..b9eed6d 100644
> --- a/drivers/mtd/spi-nor/Kconfig
> +++ b/drivers/mtd/spi-nor/Kconfig
> @@ -28,4 +28,12 @@ config SPI_FSL_QUADSPI
> This enables support for the Quad SPI controller in master mode.
> We only connect the NOR to this controller now.
>
> +config SPI_ALTERA_QUADSPI
> + tristate "Support Altera EPCQ/EPCS Flash chips"
> + depends on OF
> + help
> + This enables access to Altera EPCQ/EPCS flash chips, used for data
> + storage. See the driver source for the current list,
> + or to add other chips.
> +
> endif # MTD_SPI_NOR
> diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
> index 6a7ce14..1a36a72 100644
> --- a/drivers/mtd/spi-nor/Makefile
> +++
Re: [PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
Hi Brian,
Can you help me to review this patch of mine?
Thanks,
Nga
On Mon, Mar 16, 2015 at 4:16 PM, vn...@altera.com wrote:
From: VIET NGA DAO vn...@altera.com
Altera Quad SPI Controller is a soft IP which enables access to Altera EPCQ
and
EPCS flash chips. This patch adds driver for these devices.
Signed-off-by: VIET NGA DAO vn...@altera.com
---
v3:
- Change altera_epcq driver name to altera_quadspi for more generic name
- Implement flash name searching in altera_quadspi.c instead of spi-nor
- Edit the altra quadspi info table in spi-nor
- Remove wait_til_ready in all read,write, erase, lock, unlock functions
- Merge .h and .c into 1 file
v2:
- Change to spi_nor structure
- Add lock and unlock functions for spi_nor
- Simplify the altera_epcq_lock function
- Replace reg by compatible in device tree
---
.../devicetree/bindings/mtd/altera_quadspi.txt | 45 ++
drivers/mtd/spi-nor/Kconfig| 8 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/altera_quadspi.c | 608
+
drivers/mtd/spi-nor/spi-nor.c | 11 +
5 files changed, 673 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/altera_quadspi.txt
create mode 100644 drivers/mtd/spi-nor/altera_quadspi.c
diff --git a/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
new file mode 100644
index 000..f5bdd35
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
@@ -0,0 +1,45 @@
+* MTD Altera QUADSPI driver
+
+Required properties:
+- compatible: Should be altr,quadspi-1.0
+- reg: Address and length of the register set for the device. It contains
+ the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+ csr_base: Should contain the register configuration base address
+ data_base: Should contain the data base address
+- is-epcs: boolean type.
+ If present, the device contains EPCS flashes.
+ Otherwise, it contains EPCQ flashes.
+- #address-cells: Must be 1.
+- #size-cells: Must be 0.
+- flash device tree subnode, there must be a node with the following fields:
+ - compatible: Should contain the flash name
+ - #address-cells: please refer to /mtd/partition.txt
+ - #size-cells: please refer to /mtd/partition.txt
+ For partitions inside each flash, please refer to /mtd/partition.txt
+
+Example:
+
+ quadspi_controller_0: quadspi@0x0 {
+ compatible = altr,quadspi-1.0;
+ reg = 0x0001 0x 0x0020,
+ 0x 0x 0x0200;
+ reg-names = csr_base, data_base;
+ #address-cells = 1;
+ #size-cells = 0;
+ flash0: epcq256@0 {
+ compatible = epcq256-nonjedec;
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0 {
+ /* 16 MB for raw data. */
+ label = EPCQ Flash 0 raw
data;
+ reg = 0x0 0x100;
+ };
+ partition@100 {
+ /* 16 MB for jffs2 data. */
+ label = EPCQ Flash 0 JFFS 2;
+ reg = 0x100 0x100;
+ };
+ };
+ }; //end quadspi@0x0 (quadspi_controller_0)
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 64a4f0e..b9eed6d 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -28,4 +28,12 @@ config SPI_FSL_QUADSPI
This enables support for the Quad SPI controller in master mode.
We only connect the NOR to this controller now.
+config SPI_ALTERA_QUADSPI
+ tristate Support Altera EPCQ/EPCS Flash chips
+ depends on OF
+ help
+ This enables access to Altera EPCQ/EPCS flash chips, used for data
+ storage. See the driver source for the current list,
+ or to add other chips.
+
endif # MTD_SPI_NOR
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index 6a7ce14..1a36a72 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
[PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
From: VIET NGA DAO
Altera Quad SPI Controller is a soft IP which enables access to Altera EPCQ and
EPCS flash chips. This patch adds driver for these devices.
Signed-off-by: VIET NGA DAO
---
v3:
- Change altera_epcq driver name to altera_quadspi for more generic name
- Implement flash name searching in altera_quadspi.c instead of spi-nor
- Edit the altra quadspi info table in spi-nor
- Remove wait_til_ready in all read,write, erase, lock, unlock functions
- Merge .h and .c into 1 file
v2:
- Change to spi_nor structure
- Add lock and unlock functions for spi_nor
- Simplify the altera_epcq_lock function
- Replace reg by compatible in device tree
---
.../devicetree/bindings/mtd/altera_quadspi.txt | 45 ++
drivers/mtd/spi-nor/Kconfig| 8 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/altera_quadspi.c | 608 +
drivers/mtd/spi-nor/spi-nor.c | 11 +
5 files changed, 673 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/altera_quadspi.txt
create mode 100644 drivers/mtd/spi-nor/altera_quadspi.c
diff --git a/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
new file mode 100644
index 000..f5bdd35
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
@@ -0,0 +1,45 @@
+* MTD Altera QUADSPI driver
+
+Required properties:
+- compatible: Should be "altr,quadspi-1.0"
+- reg: Address and length of the register set for the device. It contains
+ the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+ "csr_base": Should contain the register configuration base address
+ "data_base": Should contain the data base address
+- is-epcs: boolean type.
+ If present, the device contains EPCS flashes.
+ Otherwise, it contains EPCQ flashes.
+- #address-cells: Must be <1>.
+- #size-cells: Must be <0>.
+- flash device tree subnode, there must be a node with the following fields:
+ - compatible: Should contain the flash name
+ - #address-cells: please refer to /mtd/partition.txt
+ - #size-cells: please refer to /mtd/partition.txt
+ For partitions inside each flash, please refer to /mtd/partition.txt
+
+Example:
+
+ quadspi_controller_0: quadspi@0x0 {
+ compatible = "altr,quadspi-1.0";
+ reg = <0x0001 0x 0x0020>,
+ <0x 0x 0x0200>;
+ reg-names = "csr_base", "data_base";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ flash0: epcq256@0 {
+ compatible = "epcq256-nonjedec";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ /* 16 MB for raw data. */
+ label = "EPCQ Flash 0 raw data";
+ reg = <0x0 0x100>;
+ };
+ partition@100 {
+ /* 16 MB for jffs2 data. */
+ label = "EPCQ Flash 0 JFFS 2";
+ reg = <0x100 0x100>;
+ };
+ };
+ }; //end quadspi@0x0 (quadspi_controller_0)
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 64a4f0e..b9eed6d 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -28,4 +28,12 @@ config SPI_FSL_QUADSPI
This enables support for the Quad SPI controller in master mode.
We only connect the NOR to this controller now.
+config SPI_ALTERA_QUADSPI
+ tristate "Support Altera EPCQ/EPCS Flash chips"
+ depends on OF
+ help
+ This enables access to Altera EPCQ/EPCS flash chips, used for data
+ storage. See the driver source for the current list,
+ or to add other chips.
+
endif # MTD_SPI_NOR
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index 6a7ce14..1a36a72 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o
+obj-$(CONFIG_SPI_ALTERA_QUADSPI) += altera_quadspi.o
diff --git a/drivers/mtd/spi-nor/altera_quadspi.c
b/drivers/mtd/spi-nor/altera_quadspi.c
new file mode 100644
index 000..1d178d9
---
Re: [PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
On Mon, Mar 16, 2015 at 4:35 PM, Rafał Miłecki wrote:
> On 16 March 2015 at 09:16, wrote:
>> +static struct flash_device flash_devices[] = {
>> + FLASH_ID("epcq16-nonjedec", 2, 0x15),
>> + FLASH_ID("epcq32-nonjedec", 2, 0x16),
>> + FLASH_ID("epcq64-nonjedec", 2, 0x17),
>> + FLASH_ID("epcq128-nonjedec", 2, 0x18),
>> + FLASH_ID("epcq256-nonjedec", 2, 0x19),
>> + FLASH_ID("epcq512-nonjedec", 2, 0x20),
>
> You could probably use EPCQ_OPCODE_ID
>
>
>> +
>> + FLASH_ID("epcs16-nonjedec", 1, 0x14),
>> + FLASH_ID("epcs64-nonjedec", 1, 0x16),
>> + FLASH_ID("epcs128-nonjedec", 1, 0x18),
>
> And EPCS_OPCODE_ID here.
>
Noted
>
>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
>> index 43bb552..ad0c274 100644
>> --- a/drivers/mtd/spi-nor/spi-nor.c
>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>> @@ -683,6 +683,17 @@ static const struct spi_device_id spi_nor_ids[] = {
>> { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE |
>> SPI_NOR_NO_FR) },
>> { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE |
>> SPI_NOR_NO_FR) },
>> { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE |
>> SPI_NOR_NO_FR) },
>> +
>> + /* Altera EPCQ/EPCS Flashes */
>> + { "epcq16-nonjedec", INFO(0, 0, 0x1, 32, 0) },
>> + { "epcq32-nonjedec", INFO(0, 0, 0x1, 64, 0) },
>> + { "epcq64-nonjedec", INFO(0, 0, 0x1, 128, 0) },
>> + { "epcq128-nonjedec", INFO(0, 0, 0x1, 256, 0) },
>> + { "epcq256-nonjedec", INFO(0, 0, 0x1, 512, 0) },
>> + { "epcq512-nonjedec", INFO(0, 0, 0x1, 1024, 0) },
>> + { "epcs16-nonjedec", INFO(0, 0, 0x1, 32, 0) },
>> + { "epcs64-nonjedec", INFO(0, 0, 0x1, 128, 0) },
>> + { "epcs128-nonjedec", INFO(0, 0, 0x4, 256, 0) },
>> { },
>> };
>
> But mostly, I just wanted to say I like your integration with spi-nor.
> Nice work :)
>
> --
> Rafał
Thank you. This is all thanks to you and Brian for helpful comments. I
learned a lot :)
--
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Re: [PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
On 16 March 2015 at 09:16, wrote:
> +static struct flash_device flash_devices[] = {
> + FLASH_ID("epcq16-nonjedec", 2, 0x15),
> + FLASH_ID("epcq32-nonjedec", 2, 0x16),
> + FLASH_ID("epcq64-nonjedec", 2, 0x17),
> + FLASH_ID("epcq128-nonjedec", 2, 0x18),
> + FLASH_ID("epcq256-nonjedec", 2, 0x19),
> + FLASH_ID("epcq512-nonjedec", 2, 0x20),
You could probably use EPCQ_OPCODE_ID
> +
> + FLASH_ID("epcs16-nonjedec", 1, 0x14),
> + FLASH_ID("epcs64-nonjedec", 1, 0x16),
> + FLASH_ID("epcs128-nonjedec", 1, 0x18),
And EPCS_OPCODE_ID here.
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 43bb552..ad0c274 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -683,6 +683,17 @@ static const struct spi_device_id spi_nor_ids[] = {
> { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE |
> SPI_NOR_NO_FR) },
> { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE |
> SPI_NOR_NO_FR) },
> { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE |
> SPI_NOR_NO_FR) },
> +
> + /* Altera EPCQ/EPCS Flashes */
> + { "epcq16-nonjedec", INFO(0, 0, 0x1, 32, 0) },
> + { "epcq32-nonjedec", INFO(0, 0, 0x1, 64, 0) },
> + { "epcq64-nonjedec", INFO(0, 0, 0x1, 128, 0) },
> + { "epcq128-nonjedec", INFO(0, 0, 0x1, 256, 0) },
> + { "epcq256-nonjedec", INFO(0, 0, 0x1, 512, 0) },
> + { "epcq512-nonjedec", INFO(0, 0, 0x1, 1024, 0) },
> + { "epcs16-nonjedec", INFO(0, 0, 0x1, 32, 0) },
> + { "epcs64-nonjedec", INFO(0, 0, 0x1, 128, 0) },
> + { "epcs128-nonjedec", INFO(0, 0, 0x4, 256, 0) },
> { },
> };
But mostly, I just wanted to say I like your integration with spi-nor.
Nice work :)
--
Rafał
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[PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
From: VIET NGA DAO vn...@altera.com
Altera Quad SPI Controller is a soft IP which enables access to Altera EPCQ and
EPCS flash chips. This patch adds driver for these devices.
Signed-off-by: VIET NGA DAO vn...@altera.com
---
v3:
- Change altera_epcq driver name to altera_quadspi for more generic name
- Implement flash name searching in altera_quadspi.c instead of spi-nor
- Edit the altra quadspi info table in spi-nor
- Remove wait_til_ready in all read,write, erase, lock, unlock functions
- Merge .h and .c into 1 file
v2:
- Change to spi_nor structure
- Add lock and unlock functions for spi_nor
- Simplify the altera_epcq_lock function
- Replace reg by compatible in device tree
---
.../devicetree/bindings/mtd/altera_quadspi.txt | 45 ++
drivers/mtd/spi-nor/Kconfig| 8 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/altera_quadspi.c | 608 +
drivers/mtd/spi-nor/spi-nor.c | 11 +
5 files changed, 673 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/altera_quadspi.txt
create mode 100644 drivers/mtd/spi-nor/altera_quadspi.c
diff --git a/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
new file mode 100644
index 000..f5bdd35
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
@@ -0,0 +1,45 @@
+* MTD Altera QUADSPI driver
+
+Required properties:
+- compatible: Should be altr,quadspi-1.0
+- reg: Address and length of the register set for the device. It contains
+ the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+ csr_base: Should contain the register configuration base address
+ data_base: Should contain the data base address
+- is-epcs: boolean type.
+ If present, the device contains EPCS flashes.
+ Otherwise, it contains EPCQ flashes.
+- #address-cells: Must be 1.
+- #size-cells: Must be 0.
+- flash device tree subnode, there must be a node with the following fields:
+ - compatible: Should contain the flash name
+ - #address-cells: please refer to /mtd/partition.txt
+ - #size-cells: please refer to /mtd/partition.txt
+ For partitions inside each flash, please refer to /mtd/partition.txt
+
+Example:
+
+ quadspi_controller_0: quadspi@0x0 {
+ compatible = altr,quadspi-1.0;
+ reg = 0x0001 0x 0x0020,
+ 0x 0x 0x0200;
+ reg-names = csr_base, data_base;
+ #address-cells = 1;
+ #size-cells = 0;
+ flash0: epcq256@0 {
+ compatible = epcq256-nonjedec;
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0 {
+ /* 16 MB for raw data. */
+ label = EPCQ Flash 0 raw data;
+ reg = 0x0 0x100;
+ };
+ partition@100 {
+ /* 16 MB for jffs2 data. */
+ label = EPCQ Flash 0 JFFS 2;
+ reg = 0x100 0x100;
+ };
+ };
+ }; //end quadspi@0x0 (quadspi_controller_0)
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 64a4f0e..b9eed6d 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -28,4 +28,12 @@ config SPI_FSL_QUADSPI
This enables support for the Quad SPI controller in master mode.
We only connect the NOR to this controller now.
+config SPI_ALTERA_QUADSPI
+ tristate Support Altera EPCQ/EPCS Flash chips
+ depends on OF
+ help
+ This enables access to Altera EPCQ/EPCS flash chips, used for data
+ storage. See the driver source for the current list,
+ or to add other chips.
+
endif # MTD_SPI_NOR
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index 6a7ce14..1a36a72 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o
+obj-$(CONFIG_SPI_ALTERA_QUADSPI) += altera_quadspi.o
diff --git a/drivers/mtd/spi-nor/altera_quadspi.c
b/drivers/mtd/spi-nor/altera_quadspi.c
new file mode 100644
index 000..1d178d9
--- /dev/null
+++
Re: [PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
On 16 March 2015 at 09:16, vn...@altera.com wrote:
+static struct flash_device flash_devices[] = {
+ FLASH_ID(epcq16-nonjedec, 2, 0x15),
+ FLASH_ID(epcq32-nonjedec, 2, 0x16),
+ FLASH_ID(epcq64-nonjedec, 2, 0x17),
+ FLASH_ID(epcq128-nonjedec, 2, 0x18),
+ FLASH_ID(epcq256-nonjedec, 2, 0x19),
+ FLASH_ID(epcq512-nonjedec, 2, 0x20),
You could probably use EPCQ_OPCODE_ID
+
+ FLASH_ID(epcs16-nonjedec, 1, 0x14),
+ FLASH_ID(epcs64-nonjedec, 1, 0x16),
+ FLASH_ID(epcs128-nonjedec, 1, 0x18),
And EPCS_OPCODE_ID here.
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 43bb552..ad0c274 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -683,6 +683,17 @@ static const struct spi_device_id spi_nor_ids[] = {
{ cat25c09, CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE |
SPI_NOR_NO_FR) },
{ cat25c17, CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE |
SPI_NOR_NO_FR) },
{ cat25128, CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE |
SPI_NOR_NO_FR) },
+
+ /* Altera EPCQ/EPCS Flashes */
+ { epcq16-nonjedec, INFO(0, 0, 0x1, 32, 0) },
+ { epcq32-nonjedec, INFO(0, 0, 0x1, 64, 0) },
+ { epcq64-nonjedec, INFO(0, 0, 0x1, 128, 0) },
+ { epcq128-nonjedec, INFO(0, 0, 0x1, 256, 0) },
+ { epcq256-nonjedec, INFO(0, 0, 0x1, 512, 0) },
+ { epcq512-nonjedec, INFO(0, 0, 0x1, 1024, 0) },
+ { epcs16-nonjedec, INFO(0, 0, 0x1, 32, 0) },
+ { epcs64-nonjedec, INFO(0, 0, 0x1, 128, 0) },
+ { epcs128-nonjedec, INFO(0, 0, 0x4, 256, 0) },
{ },
};
But mostly, I just wanted to say I like your integration with spi-nor.
Nice work :)
--
Rafał
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [PATCH v3] mtd:spi-nor: Add Altera Quad SPI Driver
On Mon, Mar 16, 2015 at 4:35 PM, Rafał Miłecki zaj...@gmail.com wrote:
On 16 March 2015 at 09:16, vn...@altera.com wrote:
+static struct flash_device flash_devices[] = {
+ FLASH_ID(epcq16-nonjedec, 2, 0x15),
+ FLASH_ID(epcq32-nonjedec, 2, 0x16),
+ FLASH_ID(epcq64-nonjedec, 2, 0x17),
+ FLASH_ID(epcq128-nonjedec, 2, 0x18),
+ FLASH_ID(epcq256-nonjedec, 2, 0x19),
+ FLASH_ID(epcq512-nonjedec, 2, 0x20),
You could probably use EPCQ_OPCODE_ID
+
+ FLASH_ID(epcs16-nonjedec, 1, 0x14),
+ FLASH_ID(epcs64-nonjedec, 1, 0x16),
+ FLASH_ID(epcs128-nonjedec, 1, 0x18),
And EPCS_OPCODE_ID here.
Noted
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 43bb552..ad0c274 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -683,6 +683,17 @@ static const struct spi_device_id spi_nor_ids[] = {
{ cat25c09, CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE |
SPI_NOR_NO_FR) },
{ cat25c17, CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE |
SPI_NOR_NO_FR) },
{ cat25128, CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE |
SPI_NOR_NO_FR) },
+
+ /* Altera EPCQ/EPCS Flashes */
+ { epcq16-nonjedec, INFO(0, 0, 0x1, 32, 0) },
+ { epcq32-nonjedec, INFO(0, 0, 0x1, 64, 0) },
+ { epcq64-nonjedec, INFO(0, 0, 0x1, 128, 0) },
+ { epcq128-nonjedec, INFO(0, 0, 0x1, 256, 0) },
+ { epcq256-nonjedec, INFO(0, 0, 0x1, 512, 0) },
+ { epcq512-nonjedec, INFO(0, 0, 0x1, 1024, 0) },
+ { epcs16-nonjedec, INFO(0, 0, 0x1, 32, 0) },
+ { epcs64-nonjedec, INFO(0, 0, 0x1, 128, 0) },
+ { epcs128-nonjedec, INFO(0, 0, 0x4, 256, 0) },
{ },
};
But mostly, I just wanted to say I like your integration with spi-nor.
Nice work :)
--
Rafał
Thank you. This is all thanks to you and Brian for helpful comments. I
learned a lot :)
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
