On 04/29/2014 01:31 PM, Dave Martin wrote:
> On Tue, Apr 29, 2014 at 05:36:30PM +0100, Joel Fernandes wrote:
>
> [...]
>
Sorry what I meant is, say its of Type function. What tells the firmware
to switch to THUMB?
What's typically done is a boot address register is written by
On Tue, Apr 29, 2014 at 05:36:30PM +0100, Joel Fernandes wrote:
[...]
> >> Sorry what I meant is, say its of Type function. What tells the firmware
> >> to switch to THUMB?
> >>
> >> What's typically done is a boot address register is written by the
> >> kernel, and the firmware jumps to it
> On Apr 29, 2014, at 2:17 AM, Dave Martin wrote:
>
>> On Mon, Apr 28, 2014 at 06:21:49PM +0100, Joel Fernandes wrote:
>>> On 04/28/2014 12:20 PM, Joel Fernandes wrote:
On 04/28/2014 11:43 AM, Dave Martin wrote:
> On Tue, Apr 22, 2014 at 01:31:46PM -0500, Joel Fernandes wrote:
> On
On Mon, Apr 28, 2014 at 06:21:49PM +0100, Joel Fernandes wrote:
> On 04/28/2014 12:20 PM, Joel Fernandes wrote:
> > On 04/28/2014 11:43 AM, Dave Martin wrote:
> >> On Tue, Apr 22, 2014 at 01:31:46PM -0500, Joel Fernandes wrote:
> >>> On my DRA7 system, when the kernel is built in THUMB mode, the
On Mon, Apr 28, 2014 at 06:21:49PM +0100, Joel Fernandes wrote:
On 04/28/2014 12:20 PM, Joel Fernandes wrote:
On 04/28/2014 11:43 AM, Dave Martin wrote:
On Tue, Apr 22, 2014 at 01:31:46PM -0500, Joel Fernandes wrote:
On my DRA7 system, when the kernel is built in THUMB mode, the secondary
On Apr 29, 2014, at 2:17 AM, Dave Martin dave.mar...@arm.com wrote:
On Mon, Apr 28, 2014 at 06:21:49PM +0100, Joel Fernandes wrote:
On 04/28/2014 12:20 PM, Joel Fernandes wrote:
On 04/28/2014 11:43 AM, Dave Martin wrote:
On Tue, Apr 22, 2014 at 01:31:46PM -0500, Joel Fernandes wrote:
On
On Tue, Apr 29, 2014 at 05:36:30PM +0100, Joel Fernandes wrote:
[...]
Sorry what I meant is, say its of Type function. What tells the firmware
to switch to THUMB?
What's typically done is a boot address register is written by the
kernel, and the firmware jumps to it after WFE.
On 04/29/2014 01:31 PM, Dave Martin wrote:
On Tue, Apr 29, 2014 at 05:36:30PM +0100, Joel Fernandes wrote:
[...]
Sorry what I meant is, say its of Type function. What tells the firmware
to switch to THUMB?
What's typically done is a boot address register is written by the
kernel, and
On 04/28/2014 12:20 PM, Joel Fernandes wrote:
> On 04/28/2014 11:43 AM, Dave Martin wrote:
>> On Tue, Apr 22, 2014 at 01:31:46PM -0500, Joel Fernandes wrote:
>>> On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
>>> (Cortex A15) fails to come up causing SMP boot on
On 04/28/2014 11:43 AM, Dave Martin wrote:
> On Tue, Apr 22, 2014 at 01:31:46PM -0500, Joel Fernandes wrote:
>> On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
>> (Cortex A15) fails to come up causing SMP boot on second CPU to timeout. This
>> seems to be because the
On Tue, Apr 22, 2014 at 01:31:46PM -0500, Joel Fernandes wrote:
> On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
> (Cortex A15) fails to come up causing SMP boot on second CPU to timeout. This
> seems to be because the CPU is in ARM mode once the ROM hands over
On Tue, Apr 22, 2014 at 01:31:46PM -0500, Joel Fernandes wrote:
On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
(Cortex A15) fails to come up causing SMP boot on second CPU to timeout. This
seems to be because the CPU is in ARM mode once the ROM hands over control
On 04/28/2014 11:43 AM, Dave Martin wrote:
On Tue, Apr 22, 2014 at 01:31:46PM -0500, Joel Fernandes wrote:
On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
(Cortex A15) fails to come up causing SMP boot on second CPU to timeout. This
seems to be because the CPU is
On 04/28/2014 12:20 PM, Joel Fernandes wrote:
On 04/28/2014 11:43 AM, Dave Martin wrote:
On Tue, Apr 22, 2014 at 01:31:46PM -0500, Joel Fernandes wrote:
On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
(Cortex A15) fails to come up causing SMP boot on second CPU to
On 04/22/2014 01:47 PM, Nishanth Menon wrote:
> On Tue, Apr 22, 2014 at 1:31 PM, Joel Fernandes wrote:
>> On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
> Did you mean THUMB2? omap2plus_defconfig works today with
> CONFIG_ARM_THUMB enabled..
ARM_THUMB is for user
On Tue, Apr 22, 2014 at 1:31 PM, Joel Fernandes wrote:
> On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
Did you mean THUMB2? omap2plus_defconfig works today with
CONFIG_ARM_THUMB enabled..
> (Cortex A15) fails to come up causing SMP boot on second CPU to timeout.
On Tuesday 22 April 2014 02:31 PM, Joel Fernandes wrote:
> On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
> (Cortex A15) fails to come up causing SMP boot on second CPU to timeout. This
> seems to be because the CPU is in ARM mode once the ROM hands over control to
>
On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
(Cortex A15) fails to come up causing SMP boot on second CPU to timeout. This
seems to be because the CPU is in ARM mode once the ROM hands over control to
the kernel. Switch to THUMB mode if required once the kernel is
On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
(Cortex A15) fails to come up causing SMP boot on second CPU to timeout. This
seems to be because the CPU is in ARM mode once the ROM hands over control to
the kernel. Switch to THUMB mode if required once the kernel is
On Tuesday 22 April 2014 02:31 PM, Joel Fernandes wrote:
On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
(Cortex A15) fails to come up causing SMP boot on second CPU to timeout. This
seems to be because the CPU is in ARM mode once the ROM hands over control to
the
On Tue, Apr 22, 2014 at 1:31 PM, Joel Fernandes jo...@ti.com wrote:
On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
Did you mean THUMB2? omap2plus_defconfig works today with
CONFIG_ARM_THUMB enabled..
(Cortex A15) fails to come up causing SMP boot on second CPU to
On 04/22/2014 01:47 PM, Nishanth Menon wrote:
On Tue, Apr 22, 2014 at 1:31 PM, Joel Fernandes jo...@ti.com wrote:
On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
Did you mean THUMB2? omap2plus_defconfig works today with
CONFIG_ARM_THUMB enabled..
ARM_THUMB is for
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