Re: [PATCH] ARM: dts: exynos: add CCI-400 PMU nodes support to Exynos542x SoCs

2019-04-20 Thread Willy Wolff
Indeed, many thanks Robin. Using this, values sound better. export OMP_NUM_THREADS=2 sudo --preserve-env ./perf stat -a \ -e armv7_cortex_a7/config=0x11,name=a7_cycles/ \ -e armv7_cortex_a15/config=0x11,name=a15_cycles/ \ -e armv7_cortex_a7/config=0x19,name=a7_bus/ \ -e

Re: [PATCH] ARM: dts: exynos: add CCI-400 PMU nodes support to Exynos542x SoCs

2019-04-19 Thread Robin Murphy
On 2019-04-19 6:53 pm, Willy Wolff wrote: Hi, This patch can be dropped, as it needs more work. In fact, the interrupts seems to be wrong. The interrupts suggested by Anand Moon gave the same following results. export CCI_DEV=CCI_400 export OMP_NUM_THREADS=2 sudo --preserve-env ./perf stat -a

Re: [PATCH] ARM: dts: exynos: add CCI-400 PMU nodes support to Exynos542x SoCs

2019-04-19 Thread Willy Wolff
Hi, This patch can be dropped, as it needs more work. In fact, the interrupts seems to be wrong. The interrupts suggested by Anand Moon gave the same following results. export CCI_DEV=CCI_400 export OMP_NUM_THREADS=2 sudo --preserve-env ./perf stat -a \ -e

Re: [PATCH] ARM: dts: exynos: add CCI-400 PMU nodes support to Exynos542x SoCs

2019-04-17 Thread Krzysztof Kozlowski
On Wed, 17 Apr 2019 at 06:26, Anand Moon wrote: > > Hi Krzysztof, > > On Tue, 16 Apr 2019 at 15:49, Krzysztof Kozlowski wrote: > > > > On Mon, 15 Apr 2019 at 14:24, Anand Moon wrote: > > > Cache Coherent Interface (CCI) among Cortex-A15 and Cortex-A7, G2D, G3D > > > and SSS > > > > > > Level 0

Re: [PATCH] ARM: dts: exynos: add CCI-400 PMU nodes support to Exynos542x SoCs

2019-04-16 Thread Anand Moon
Hi Krzysztof, On Tue, 16 Apr 2019 at 15:49, Krzysztof Kozlowski wrote: > > On Mon, 15 Apr 2019 at 14:24, Anand Moon wrote: > > Cache Coherent Interface (CCI) among Cortex-A15 and Cortex-A7, G2D, G3D and > > SSS > > > > Level 0 > CPU blocks such as Cortex-A15 (CA15), Cortex-A7 (CA7) are > >

Re: [PATCH] ARM: dts: exynos: add CCI-400 PMU nodes support to Exynos542x SoCs

2019-04-16 Thread Krzysztof Kozlowski
On Mon, 15 Apr 2019 at 14:24, Anand Moon wrote: > Cache Coherent Interface (CCI) among Cortex-A15 and Cortex-A7, G2D, G3D and > SSS > > Level 0 > CPU blocks such as Cortex-A15 (CA15), Cortex-A7 (CA7) are > joined as the member of Level 0 CCI bus > > Level 1 > Display engine block (DISP) and 2D

Re: [PATCH] ARM: dts: exynos: add CCI-400 PMU nodes support to Exynos542x SoCs

2019-04-15 Thread Anand Moon
Hi Willy, On Fri, 12 Apr 2019 at 22:55, Willy Wolff wrote: > > Add device tree entries for PMU of ARM CCI-400. > > $ sudo ./perf stat -a -C 0 -e CCI_400/config=0xff,name=cycles/ sleep 1 > > Performance counter stats for 'system wide': > >420,303,619 cycles > >1.019058775

[PATCH] ARM: dts: exynos: add CCI-400 PMU nodes support to Exynos542x SoCs

2019-04-12 Thread Willy Wolff
Add device tree entries for PMU of ARM CCI-400. $ sudo ./perf stat -a -C 0 -e CCI_400/config=0xff,name=cycles/ sleep 1 Performance counter stats for 'system wide': 420,303,619 cycles 1.019058775 seconds time elapsed Tested on Odroid-xu3 and 4. Signed-off-by: Willy Wolff