om'; 'linux-
> ker...@vger.kernel.org'
> Subject: Re: [alsa-devel] [PATCH] ASoC: Add support for multi register mux
>
> * PGP Signed by an unknown key
>
> On Mon, Mar 31, 2014 at 01:55:52PM +0200, Lars-Peter Clausen wrote:
> > On 03/31/2014 01:21 PM, Mark Brown wrote:
>
...@vger.kernel.org'
Subject: Re: [alsa-devel] [PATCH] ASoC: Add support for multi register mux
* PGP Signed by an unknown key
On Mon, Mar 31, 2014 at 01:55:52PM +0200, Lars-Peter Clausen wrote:
On 03/31/2014 01:21 PM, Mark Brown wrote:
The above is a bit confusing... partly this is because
On Mon, Mar 31, 2014 at 01:55:52PM +0200, Lars-Peter Clausen wrote:
> On 03/31/2014 01:21 PM, Mark Brown wrote:
> >The above is a bit confusing... partly this is because of a lack of
> >context (what is MULTI_MUX_INPUT_OFFSET?) and partly because it isn't
> >entirely obvious that stopping as
On 03/31/2014 01:21 PM, Mark Brown wrote:
On Sat, Mar 29, 2014 at 11:12:30PM -0700, Arun Shamanna Lakshmi wrote:
Fix your mailer to word wrap within paragraphs, your mails are
excessively hard to read.
I'm not sure I understand how that MUX_OFFSET would work. To get the
selected mux output
On Sat, Mar 29, 2014 at 11:12:30PM -0700, Arun Shamanna Lakshmi wrote:
Fix your mailer to word wrap within paragraphs, your mails are
excessively hard to read.
> > I'm not sure I understand how that MUX_OFFSET would work. To get the
> > selected mux output you can use the ffs instruction.
> >
On Sat, Mar 29, 2014 at 11:12:30PM -0700, Arun Shamanna Lakshmi wrote:
Fix your mailer to word wrap within paragraphs, your mails are
excessively hard to read.
I'm not sure I understand how that MUX_OFFSET would work. To get the
selected mux output you can use the ffs instruction.
On 03/31/2014 01:21 PM, Mark Brown wrote:
On Sat, Mar 29, 2014 at 11:12:30PM -0700, Arun Shamanna Lakshmi wrote:
Fix your mailer to word wrap within paragraphs, your mails are
excessively hard to read.
I'm not sure I understand how that MUX_OFFSET would work. To get the
selected mux output
On Mon, Mar 31, 2014 at 01:55:52PM +0200, Lars-Peter Clausen wrote:
On 03/31/2014 01:21 PM, Mark Brown wrote:
The above is a bit confusing... partly this is because of a lack of
context (what is MULTI_MUX_INPUT_OFFSET?) and partly because it isn't
entirely obvious that stopping as soon as we
g'; 'ti...@suse.de';
> 'linux-kernel@vger.kernel.org'
> Subject: Re: [alsa-devel] [PATCH] ASoC: Add support for multi register mux
>
> On 03/29/2014 03:30 AM, Songhee Baek wrote:
> >> -Original Message-
> >> From: Songhee Baek
> >> Sent: Friday, March 28,
-kernel@vger.kernel.org'
Subject: Re: [alsa-devel] [PATCH] ASoC: Add support for multi register mux
On 03/29/2014 03:30 AM, Songhee Baek wrote:
-Original Message-
From: Songhee Baek
Sent: Friday, March 28, 2014 11:10 AM
To: 'Lars-Peter Clausen'
Cc: Arun Shamanna Lakshmi; 'lgirdw
';
'linux-kernel@vger.kernel.org'
Subject: RE: [alsa-devel] [PATCH] ASoC: Add support for multi register mux
On 03/26/2014 11:41 PM, Songhee Baek wrote:
On 03/26/2014 01:02 AM, Arun Shamanna Lakshmi wrote:
The way you describe this it seems to me that a value array for
this kind of mux would
';
'linux-kernel@vger.kernel.org'
Subject: RE: [alsa-devel] [PATCH] ASoC: Add support for multi register mux
On 03/26/2014 11:41 PM, Songhee Baek wrote:
On 03/26/2014 01:02 AM, Arun Shamanna Lakshmi wrote:
The way you describe this it seems to me that a value array for
this kind of mux would
ernel@vger.kernel.org'
> Subject: RE: [alsa-devel] [PATCH] ASoC: Add support for multi register mux
>
>
> > > On 03/26/2014 11:41 PM, Songhee Baek wrote:
> > > >> On 03/26/2014 01:02 AM, Arun Shamanna Lakshmi wrote:
> > > >>
> > > >>
> > On 03/26/2014 11:41 PM, Songhee Baek wrote:
> > >> On 03/26/2014 01:02 AM, Arun Shamanna Lakshmi wrote:
> > >>
> > >> The way you describe this it seems to me that a value array for
> > >> this kind of mux would look like.
> > >>
> > >> 0x, 0x, 0x0001
> > >> 0x,
On 03/26/2014 11:41 PM, Songhee Baek wrote:
On 03/26/2014 01:02 AM, Arun Shamanna Lakshmi wrote:
The way you describe this it seems to me that a value array for
this kind of mux would look like.
0x, 0x, 0x0001
0x, 0x, 0x0002
'
Subject: RE: [alsa-devel] [PATCH] ASoC: Add support for multi register mux
On 03/26/2014 11:41 PM, Songhee Baek wrote:
On 03/26/2014 01:02 AM, Arun Shamanna Lakshmi wrote:
The way you describe this it seems to me that a value array for
this kind of mux would look like
de;
> linux-kernel@vger.kernel.org
> Subject: Re: [alsa-devel] [PATCH] ASoC: Add support for multi register mux
>
> On 03/26/2014 11:41 PM, Songhee Baek wrote:
> >> -Original Message-
> >> From: Lars-Peter Clausen [mailto:l...@metafoo.de]
> >> Sent:
-project.org; ti...@suse.de; linux-
ker...@vger.kernel.org
Subject: Re: [alsa-devel] [PATCH] ASoC: Add support for multi register mux
On 03/26/2014 01:02 AM, Arun Shamanna Lakshmi wrote:
If the mux uses 1 bit position per input, and requires to set one
single bit at a time, then an N bit register can support
-project.org; ti...@suse.de; linux-
ker...@vger.kernel.org
Subject: Re: [alsa-devel] [PATCH] ASoC: Add support for multi register mux
On 03/26/2014 01:02 AM, Arun Shamanna Lakshmi wrote:
If the mux uses 1 bit position per input, and requires to set one
single bit at a time, then an N bit register can support
@vger.kernel.org
Subject: Re: [alsa-devel] [PATCH] ASoC: Add support for multi register mux
On 03/26/2014 11:41 PM, Songhee Baek wrote:
-Original Message-
From: Lars-Peter Clausen [mailto:l...@metafoo.de]
Sent: Wednesday, March 26, 2014 12:39 PM
To: Arun Shamanna Lakshmi
Cc: lgirdw
roject.org;
> swar...@wwwdotorg.org; ti...@suse.de; lgirdw...@gmail.com; linux-
> ker...@vger.kernel.org
> Subject: Re: [alsa-devel] [PATCH] ASoC: Add support for multi register mux
>
> * PGP Signed by an unknown key
>
> On Wed, Mar 26, 2014 at 08:38:47PM +0100, Lars-Peter Clausen
On Tue, Mar 25, 2014 at 05:02:35PM -0700, Arun Shamanna Lakshmi wrote:
> + }
> + if (!match) {
> + dev_err(codec->dev, "ASoC: Failed to find matched enum
> value\n");
> + return -EINVAL;
> + } else
> + ucontrol->value.enumerated.item[0] = i;
On Wed, Mar 26, 2014 at 08:38:47PM +0100, Lars-Peter Clausen wrote:
> On 03/26/2014 01:02 AM, Arun Shamanna Lakshmi wrote:
> The way you describe this it seems to me that a value array for this kind of
> mux would look like.
> 0x, 0x, 0x0001
> 0x, 0x,
e.de; linux-
> ker...@vger.kernel.org
> Subject: Re: [alsa-devel] [PATCH] ASoC: Add support for multi register mux
>
> On 03/26/2014 01:02 AM, Arun Shamanna Lakshmi wrote:
> > If the mux uses 1 bit position per input, and requires to set one
> > single bit at a time, then an N b
On 03/26/2014 01:02 AM, Arun Shamanna Lakshmi wrote:
If the mux uses 1 bit position per input, and requires to set one
single bit at a time, then an N bit register can support up to N
inputs. In more recent Tegra chips, we have at least greater than
64 inputs which requires at least 2 .reg
On 03/26/2014 01:02 AM, Arun Shamanna Lakshmi wrote:
If the mux uses 1 bit position per input, and requires to set one
single bit at a time, then an N bit register can support up to N
inputs. In more recent Tegra chips, we have at least greater than
64 inputs which requires at least 2 .reg
...@vger.kernel.org
Subject: Re: [alsa-devel] [PATCH] ASoC: Add support for multi register mux
On 03/26/2014 01:02 AM, Arun Shamanna Lakshmi wrote:
If the mux uses 1 bit position per input, and requires to set one
single bit at a time, then an N bit register can support up to N
inputs. In more recent
On Wed, Mar 26, 2014 at 08:38:47PM +0100, Lars-Peter Clausen wrote:
On 03/26/2014 01:02 AM, Arun Shamanna Lakshmi wrote:
The way you describe this it seems to me that a value array for this kind of
mux would look like.
0x, 0x, 0x0001
0x, 0x, 0x0002
On Tue, Mar 25, 2014 at 05:02:35PM -0700, Arun Shamanna Lakshmi wrote:
+ }
+ if (!match) {
+ dev_err(codec-dev, ASoC: Failed to find matched enum
value\n);
+ return -EINVAL;
+ } else
+ ucontrol-value.enumerated.item[0] = i;
Coding style
...@wwwdotorg.org; ti...@suse.de; lgirdw...@gmail.com; linux-
ker...@vger.kernel.org
Subject: Re: [alsa-devel] [PATCH] ASoC: Add support for multi register mux
* PGP Signed by an unknown key
On Wed, Mar 26, 2014 at 08:38:47PM +0100, Lars-Peter Clausen wrote:
On 03/26/2014 01:02 AM, Arun Shamanna Lakshmi
If the mux uses 1 bit position per input, and requires to set one
single bit at a time, then an N bit register can support up to N
inputs. In more recent Tegra chips, we have at least greater than
64 inputs which requires at least 2 .reg fields in struct soc_enum.
Signed-off-by: Arun Shamanna
If the mux uses 1 bit position per input, and requires to set one
single bit at a time, then an N bit register can support up to N
inputs. In more recent Tegra chips, we have at least greater than
64 inputs which requires at least 2 .reg fields in struct soc_enum.
Signed-off-by: Arun Shamanna
On Thu, Mar 20, 2014 at 08:40:54PM +0100, Lars-Peter Clausen wrote:
> On 03/20/2014 08:05 PM, Lars-Peter Clausen wrote:
> >It might make sense to add special code for supported muxes with a one-hot
> >encoding instead of using a value mux. Having an large array where each
> >entry is just 1<
On Thu, Mar 20, 2014 at 08:40:54PM +0100, Lars-Peter Clausen wrote:
On 03/20/2014 08:05 PM, Lars-Peter Clausen wrote:
It might make sense to add special code for supported muxes with a one-hot
encoding instead of using a value mux. Having an large array where each
entry is just 1n is a bit
On 03/20/2014 08:05 PM, Lars-Peter Clausen wrote:
On 03/20/2014 07:36 PM, Mark Brown wrote:
On Thu, Mar 20, 2014 at 12:20:17PM -0600, Stephen Warren wrote:
On 03/20/2014 05:48 AM, Mark Brown wrote:
On Wed, Mar 19, 2014 at 04:44:00PM -0700, Arun Shamanna Lakshmi wrote:
If each bit of a 32
On 03/20/2014 07:36 PM, Mark Brown wrote:
On Thu, Mar 20, 2014 at 12:20:17PM -0600, Stephen Warren wrote:
On 03/20/2014 05:48 AM, Mark Brown wrote:
On Wed, Mar 19, 2014 at 04:44:00PM -0700, Arun Shamanna Lakshmi wrote:
If each bit of a 32 bit register maps to an input of a mux, then with
On Thu, Mar 20, 2014 at 12:20:17PM -0600, Stephen Warren wrote:
> On 03/20/2014 05:48 AM, Mark Brown wrote:
> > On Wed, Mar 19, 2014 at 04:44:00PM -0700, Arun Shamanna Lakshmi wrote:
> >> If each bit of a 32 bit register maps to an input of a mux, then with
> >> the current 'soc_enum' structure
On 03/20/2014 05:48 AM, Mark Brown wrote:
> On Wed, Mar 19, 2014 at 04:44:00PM -0700, Arun Shamanna Lakshmi wrote:
>
> Don't top post and fix your mailer to word wrap within paragraphs, your
> mail is very hard to read.
>
>> If each bit of a 32 bit register maps to an input of a mux, then with
On Wed, Mar 19, 2014 at 04:44:00PM -0700, Arun Shamanna Lakshmi wrote:
Don't top post and fix your mailer to word wrap within paragraphs, your
mail is very hard to read.
> If each bit of a 32 bit register maps to an input of a mux, then with
> the current 'soc_enum' structure we cannot have more
On Wed, Mar 19, 2014 at 04:44:00PM -0700, Arun Shamanna Lakshmi wrote:
Don't top post and fix your mailer to word wrap within paragraphs, your
mail is very hard to read.
If each bit of a 32 bit register maps to an input of a mux, then with
the current 'soc_enum' structure we cannot have more
On 03/20/2014 05:48 AM, Mark Brown wrote:
On Wed, Mar 19, 2014 at 04:44:00PM -0700, Arun Shamanna Lakshmi wrote:
Don't top post and fix your mailer to word wrap within paragraphs, your
mail is very hard to read.
If each bit of a 32 bit register maps to an input of a mux, then with
the
On Thu, Mar 20, 2014 at 12:20:17PM -0600, Stephen Warren wrote:
On 03/20/2014 05:48 AM, Mark Brown wrote:
On Wed, Mar 19, 2014 at 04:44:00PM -0700, Arun Shamanna Lakshmi wrote:
If each bit of a 32 bit register maps to an input of a mux, then with
the current 'soc_enum' structure we cannot
On 03/20/2014 07:36 PM, Mark Brown wrote:
On Thu, Mar 20, 2014 at 12:20:17PM -0600, Stephen Warren wrote:
On 03/20/2014 05:48 AM, Mark Brown wrote:
On Wed, Mar 19, 2014 at 04:44:00PM -0700, Arun Shamanna Lakshmi wrote:
If each bit of a 32 bit register maps to an input of a mux, then with
On 03/20/2014 08:05 PM, Lars-Peter Clausen wrote:
On 03/20/2014 07:36 PM, Mark Brown wrote:
On Thu, Mar 20, 2014 at 12:20:17PM -0600, Stephen Warren wrote:
On 03/20/2014 05:48 AM, Mark Brown wrote:
On Wed, Mar 19, 2014 at 04:44:00PM -0700, Arun Shamanna Lakshmi wrote:
If each bit of a 32
to:broo...@kernel.org]
Sent: Tuesday, March 18, 2014 5:00 PM
To: Arun Shamanna Lakshmi
Cc: lgirdw...@gmail.com; pe...@perex.cz; ti...@suse.de;
alsa-de...@alsa-project.org; linux-kernel@vger.kernel.org; Songhee Baek
Subject: Re: [PATCH] ASoC: Add support for multi register mux
* PGP Signe
...@gmail.com; pe...@perex.cz; ti...@suse.de;
alsa-de...@alsa-project.org; linux-kernel@vger.kernel.org; Songhee Baek
Subject: Re: [PATCH] ASoC: Add support for multi register mux
* PGP Signed by an unknown key
On Tue, Mar 18, 2014 at 04:51:32PM -0700, Arun Shamanna Lakshmi wrote:
Currently soc_enum
On Tue, Mar 18, 2014 at 04:51:32PM -0700, Arun Shamanna Lakshmi wrote:
> Currently soc_enum structure supports only 2 registers (reg, reg2)
> for kcontrol. However, it is possible to have multiple registers
> per mux. This change allows us to control these multiple registers.
I'd want to see a
Currently soc_enum structure supports only 2 registers (reg, reg2)
for kcontrol. However, it is possible to have multiple registers
per mux. This change allows us to control these multiple registers.
Signed-off-by: Arun Shamanna Lakshmi
Signed-off-by: Songhee Baek
---
include/sound/soc.h |
Currently soc_enum structure supports only 2 registers (reg, reg2)
for kcontrol. However, it is possible to have multiple registers
per mux. This change allows us to control these multiple registers.
Signed-off-by: Arun Shamanna Lakshmi ar...@nvidia.com
Signed-off-by: Songhee Baek
On Tue, Mar 18, 2014 at 04:51:32PM -0700, Arun Shamanna Lakshmi wrote:
Currently soc_enum structure supports only 2 registers (reg, reg2)
for kcontrol. However, it is possible to have multiple registers
per mux. This change allows us to control these multiple registers.
I'd want to see a user
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