On Wed, Aug 17, 2016 at 10:44:56AM +0200, Johannes Thumshirn wrote:
> On Mon, Aug 15, 2016 at 09:08:49PM +0200, Tillmann Heidsieck wrote:
> > According to the reference manual of MPC8572 and T4240, bit 31 of
> > PEX_ERR_CAP_STAT is W1C (write 1 to clear).
> > This patch adds the corresponding
On Wed, Aug 17, 2016 at 10:44:56AM +0200, Johannes Thumshirn wrote:
> On Mon, Aug 15, 2016 at 09:08:49PM +0200, Tillmann Heidsieck wrote:
> > According to the reference manual of MPC8572 and T4240, bit 31 of
> > PEX_ERR_CAP_STAT is W1C (write 1 to clear).
> > This patch adds the corresponding
On Mon, Aug 15, 2016 at 09:08:49PM +0200, Tillmann Heidsieck wrote:
> According to the reference manual of MPC8572 and T4240, bit 31 of
> PEX_ERR_CAP_STAT is W1C (write 1 to clear).
> This patch adds the corresponding write to PEX_ERR_CAP_STAT in order to
> fix the PCIe error capture.
>
> Tested
On Mon, Aug 15, 2016 at 09:08:49PM +0200, Tillmann Heidsieck wrote:
> According to the reference manual of MPC8572 and T4240, bit 31 of
> PEX_ERR_CAP_STAT is W1C (write 1 to clear).
> This patch adds the corresponding write to PEX_ERR_CAP_STAT in order to
> fix the PCIe error capture.
>
> Tested
According to the reference manual of MPC8572 and T4240, bit 31 of
PEX_ERR_CAP_STAT is W1C (write 1 to clear).
This patch adds the corresponding write to PEX_ERR_CAP_STAT in order to
fix the PCIe error capture.
Tested on a T4240 processor.
Signed-off-by: Tillmann Heidsieck
According to the reference manual of MPC8572 and T4240, bit 31 of
PEX_ERR_CAP_STAT is W1C (write 1 to clear).
This patch adds the corresponding write to PEX_ERR_CAP_STAT in order to
fix the PCIe error capture.
Tested on a T4240 processor.
Signed-off-by: Tillmann Heidsieck
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