The timing loop used for CPU speed detection on SH takes 5 cycles instead
of 4 on SH3 if it's not word-aligned. SH4 may want recalibrating, given the
'I don't know why, but it appears to take 6 cycles' comment.
Index: arch/sh/kernel/time.c
===================================================================
RCS file: /inst/cvs/linux/arch/sh/kernel/Attic/time.c,v
retrieving revision 1.1.2.13
diff -u -r1.1.2.13 time.c
--- arch/sh/kernel/time.c 2000/10/04 12:29:25 1.1.2.13
+++ arch/sh/kernel/time.c 2000/10/19 07:42:31
@@ -337,6 +337,7 @@
do {} while (ctrl_inb(R64CNT) != 0);
ctrl_outb(RCR1_CIE, RCR1); /* Enable carry interrupt */
asm volatile(
+ ".align 2\n\t"
"1:\t"
"tst %1,%1\n\t"
"bt/s 1b\n\t"
--
dwmw2
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