Re: [PATCH] MIPS: mscc: ocelot: add MIIM1 bus

2018-07-26 Thread Paul Burton
Hi Quentin, On Wed, Jul 25, 2018 at 02:22:41PM +0200, Quentin Schulz wrote: > There is an additional MIIM (MDIO) bus in this SoC so let's declare it > in the dtsi. > > This bus requires GPIO 14 and 15 pins that need to be muxed. There is no > support for internal PHY reset on this bus on the

Re: [PATCH] MIPS: mscc: ocelot: add MIIM1 bus

2018-07-26 Thread Paul Burton
Hi Quentin, On Wed, Jul 25, 2018 at 02:22:41PM +0200, Quentin Schulz wrote: > There is an additional MIIM (MDIO) bus in this SoC so let's declare it > in the dtsi. > > This bus requires GPIO 14 and 15 pins that need to be muxed. There is no > support for internal PHY reset on this bus on the

Re: [PATCH] MIPS: mscc: ocelot: add MIIM1 bus

2018-07-25 Thread Alexandre Belloni
On 25/07/2018 14:22:41+0200, Quentin Schulz wrote: > There is an additional MIIM (MDIO) bus in this SoC so let's declare it > in the dtsi. > > This bus requires GPIO 14 and 15 pins that need to be muxed. There is no > support for internal PHY reset on this bus on the contrary of MIIM0 so > there

Re: [PATCH] MIPS: mscc: ocelot: add MIIM1 bus

2018-07-25 Thread Alexandre Belloni
On 25/07/2018 14:22:41+0200, Quentin Schulz wrote: > There is an additional MIIM (MDIO) bus in this SoC so let's declare it > in the dtsi. > > This bus requires GPIO 14 and 15 pins that need to be muxed. There is no > support for internal PHY reset on this bus on the contrary of MIIM0 so > there

[PATCH] MIPS: mscc: ocelot: add MIIM1 bus

2018-07-25 Thread Quentin Schulz
There is an additional MIIM (MDIO) bus in this SoC so let's declare it in the dtsi. This bus requires GPIO 14 and 15 pins that need to be muxed. There is no support for internal PHY reset on this bus on the contrary of MIIM0 so there is only one register address space and not two. Signed-off-by:

[PATCH] MIPS: mscc: ocelot: add MIIM1 bus

2018-07-25 Thread Quentin Schulz
There is an additional MIIM (MDIO) bus in this SoC so let's declare it in the dtsi. This bus requires GPIO 14 and 15 pins that need to be muxed. There is no support for internal PHY reset on this bus on the contrary of MIIM0 so there is only one register address space and not two. Signed-off-by: