Re: [PATCH] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2

2018-08-31 Thread Nishanth Menon
On 15:56-20180828, Kishon Vijay Abraham I wrote: [...] > cbass_mcu: interconnect@2838 { > compatible = "simple-bus"; > #address-cells = <1>; > #size-cells = <1>; > - ranges = <0x2838

Re: [PATCH] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2

2018-08-31 Thread Nishanth Menon
On 15:56-20180828, Kishon Vijay Abraham I wrote: [...] > cbass_mcu: interconnect@2838 { > compatible = "simple-bus"; > #address-cells = <1>; > #size-cells = <1>; > - ranges = <0x2838

Re: [PATCH] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2

2018-08-31 Thread Vignesh R
Kishon, On 28-Aug-18 9:55 PM, Tony Lindgren wrote: > * Kishon Vijay Abraham I [180828 10:31]: >> AM65 has two PCIe controllers and each PCIe controller has '2' address >> spaces one within the 4GB address space of the SoC and the other above >> the 4GB address space of the SoC in addition to the

Re: [PATCH] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2

2018-08-31 Thread Vignesh R
Kishon, On 28-Aug-18 9:55 PM, Tony Lindgren wrote: > * Kishon Vijay Abraham I [180828 10:31]: >> AM65 has two PCIe controllers and each PCIe controller has '2' address >> spaces one within the 4GB address space of the SoC and the other above >> the 4GB address space of the SoC in addition to the

Re: [PATCH] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2

2018-08-28 Thread Tony Lindgren
* Kishon Vijay Abraham I [180828 10:31]: > AM65 has two PCIe controllers and each PCIe controller has '2' address > spaces one within the 4GB address space of the SoC and the other above > the 4GB address space of the SoC in addition to the register space. The > size of the address space above

Re: [PATCH] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2

2018-08-28 Thread Tony Lindgren
* Kishon Vijay Abraham I [180828 10:31]: > AM65 has two PCIe controllers and each PCIe controller has '2' address > spaces one within the 4GB address space of the SoC and the other above > the 4GB address space of the SoC in addition to the register space. The > size of the address space above

[PATCH] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2

2018-08-28 Thread Kishon Vijay Abraham I
AM65 has two PCIe controllers and each PCIe controller has '2' address spaces one within the 4GB address space of the SoC and the other above the 4GB address space of the SoC in addition to the register space. The size of the address space above the 4GB SoC address space is 4GB. These address

[PATCH] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2

2018-08-28 Thread Kishon Vijay Abraham I
AM65 has two PCIe controllers and each PCIe controller has '2' address spaces one within the 4GB address space of the SoC and the other above the 4GB address space of the SoC in addition to the register space. The size of the address space above the 4GB SoC address space is 4GB. These address