On Sat, Sep 28, 2013 at 01:40:27AM +0200, Oliver Neukum wrote:
> On Fri, 2013-09-27 at 16:50 +0200, Peter Zijlstra wrote:
> > On Fri, Sep 27, 2013 at 07:34:55AM -0700, Joe Perches wrote:
> > > That would make it seem as if all barriers are SMP no?
> >
> > I would think any memory barrier is
On Sat, Sep 28, 2013 at 01:40:27AM +0200, Oliver Neukum wrote:
On Fri, 2013-09-27 at 16:50 +0200, Peter Zijlstra wrote:
On Fri, Sep 27, 2013 at 07:34:55AM -0700, Joe Perches wrote:
That would make it seem as if all barriers are SMP no?
I would think any memory barrier is ordering
On Fri, 2013-09-27 at 16:50 +0200, Peter Zijlstra wrote:
> On Fri, Sep 27, 2013 at 07:34:55AM -0700, Joe Perches wrote:
> > That would make it seem as if all barriers are SMP no?
>
> I would think any memory barrier is ordering against someone else; if
> not smp then a device/hardware -- like for
On Fri, Sep 27, 2013 at 05:34:34PM +0200, Peter Zijlstra wrote:
> On Fri, Sep 27, 2013 at 08:17:50AM -0700, Paul E. McKenney wrote:
> > > Barriers are fundamentally about order; and order only makes sense if
> > > there's more than 1 party to the game.
> >
> > Oddly enough, there is one exception
On Fri, Sep 27, 2013 at 08:17:50AM -0700, Paul E. McKenney wrote:
> > Barriers are fundamentally about order; and order only makes sense if
> > there's more than 1 party to the game.
>
> Oddly enough, there is one exception that proves the rule... On Itanium,
> suppose we have the following
On Fri, Sep 27, 2013 at 04:50:07PM +0200, Peter Zijlstra wrote:
> On Fri, Sep 27, 2013 at 07:34:55AM -0700, Joe Perches wrote:
> > That would make it seem as if all barriers are SMP no?
>
> I would think any memory barrier is ordering against someone else; if
> not smp then a device/hardware --
On Fri, Sep 27, 2013 at 07:34:55AM -0700, Joe Perches wrote:
> That would make it seem as if all barriers are SMP no?
I would think any memory barrier is ordering against someone else; if
not smp then a device/hardware -- like for instance the hardware page
table walker.
Barriers are
On Fri, 2013-09-27 at 16:26 +0200, Peter Zijlstra wrote:
> On Fri, Sep 27, 2013 at 07:14:17AM -0700, Joe Perches wrote:
> > Peter Zijlstra prefers that comments be required near uses
> > of memory barriers.
> >
> > Change the message level for memory barrier uses from a
> > --strict test only to
On Fri, Sep 27, 2013 at 07:14:17AM -0700, Joe Perches wrote:
> Peter Zijlstra prefers that comments be required near uses
> of memory barriers.
>
> Change the message level for memory barrier uses from a
> --strict test only to a normal WARN so it's always emitted.
>
> This might produce false
Peter Zijlstra prefers that comments be required near uses
of memory barriers.
Change the message level for memory barrier uses from a
--strict test only to a normal WARN so it's always emitted.
This might produce false positives around insertions of
memory barriers when a comment is outside the
Peter Zijlstra prefers that comments be required near uses
of memory barriers.
Change the message level for memory barrier uses from a
--strict test only to a normal WARN so it's always emitted.
This might produce false positives around insertions of
memory barriers when a comment is outside the
On Fri, Sep 27, 2013 at 07:14:17AM -0700, Joe Perches wrote:
Peter Zijlstra prefers that comments be required near uses
of memory barriers.
Change the message level for memory barrier uses from a
--strict test only to a normal WARN so it's always emitted.
This might produce false
On Fri, 2013-09-27 at 16:26 +0200, Peter Zijlstra wrote:
On Fri, Sep 27, 2013 at 07:14:17AM -0700, Joe Perches wrote:
Peter Zijlstra prefers that comments be required near uses
of memory barriers.
Change the message level for memory barrier uses from a
--strict test only to a normal
On Fri, Sep 27, 2013 at 07:34:55AM -0700, Joe Perches wrote:
That would make it seem as if all barriers are SMP no?
I would think any memory barrier is ordering against someone else; if
not smp then a device/hardware -- like for instance the hardware page
table walker.
Barriers are
On Fri, Sep 27, 2013 at 04:50:07PM +0200, Peter Zijlstra wrote:
On Fri, Sep 27, 2013 at 07:34:55AM -0700, Joe Perches wrote:
That would make it seem as if all barriers are SMP no?
I would think any memory barrier is ordering against someone else; if
not smp then a device/hardware -- like
On Fri, Sep 27, 2013 at 08:17:50AM -0700, Paul E. McKenney wrote:
Barriers are fundamentally about order; and order only makes sense if
there's more than 1 party to the game.
Oddly enough, there is one exception that proves the rule... On Itanium,
suppose we have the following code, with
On Fri, Sep 27, 2013 at 05:34:34PM +0200, Peter Zijlstra wrote:
On Fri, Sep 27, 2013 at 08:17:50AM -0700, Paul E. McKenney wrote:
Barriers are fundamentally about order; and order only makes sense if
there's more than 1 party to the game.
Oddly enough, there is one exception that
On Fri, 2013-09-27 at 16:50 +0200, Peter Zijlstra wrote:
On Fri, Sep 27, 2013 at 07:34:55AM -0700, Joe Perches wrote:
That would make it seem as if all barriers are SMP no?
I would think any memory barrier is ordering against someone else; if
not smp then a device/hardware -- like for
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