Hi Martin
On 11/07/17 06:03, Martin Blumenstingl wrote:
> Hi Yixun,
>
> On Mon, Nov 6, 2017 at 10:31 AM, Yixun Lan wrote:
>> Hi Neil:
>>
>>
>> On 11/06/17 16:57, Neil Armstrong wrote:
>>> On 06/11/2017 08:52, Yixun Lan wrote:
According to the datasheet, in
Hi Martin
On 11/07/17 06:03, Martin Blumenstingl wrote:
> Hi Yixun,
>
> On Mon, Nov 6, 2017 at 10:31 AM, Yixun Lan wrote:
>> Hi Neil:
>>
>>
>> On 11/06/17 16:57, Neil Armstrong wrote:
>>> On 06/11/2017 08:52, Yixun Lan wrote:
According to the datasheet, in Meson-GXBB/GXL series,
The
Hi Yixun,
On Mon, Nov 6, 2017 at 10:31 AM, Yixun Lan wrote:
> Hi Neil:
>
>
> On 11/06/17 16:57, Neil Armstrong wrote:
>> On 06/11/2017 08:52, Yixun Lan wrote:
>>> According to the datasheet, in Meson-GXBB/GXL series,
>>> The clock gate bit for SARADC is HHI_GCLK_MPEG2
Hi Yixun,
On Mon, Nov 6, 2017 at 10:31 AM, Yixun Lan wrote:
> Hi Neil:
>
>
> On 11/06/17 16:57, Neil Armstrong wrote:
>> On 06/11/2017 08:52, Yixun Lan wrote:
>>> According to the datasheet, in Meson-GXBB/GXL series,
>>> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
>>> while clock
On Mon, 2017-11-06 at 17:38 +0800, Yixun Lan wrote:
> > * Is it an error in the published datasheets ?
>
> then, I think the published datasheet need to be updated.
This needs to be clearly explained in your patch description/comment, or maybe
directly in the code.
On Mon, 2017-11-06 at 17:38 +0800, Yixun Lan wrote:
> > * Is it an error in the published datasheets ?
>
> then, I think the published datasheet need to be updated.
This needs to be clearly explained in your patch description/comment, or maybe
directly in the code.
Hi Jerome:
On 11/06/17 17:10, Jerome Brunet wrote:
> On Mon, 2017-11-06 at 15:52 +0800, Yixun Lan wrote:
>> According to the datasheet, in Meson-GXBB/GXL series,
>> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
>> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
>>
>> Test
Hi Jerome:
On 11/06/17 17:10, Jerome Brunet wrote:
> On Mon, 2017-11-06 at 15:52 +0800, Yixun Lan wrote:
>> According to the datasheet, in Meson-GXBB/GXL series,
>> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
>> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
>>
>> Test
On Mon, 2017-11-06 at 17:38 +0800, Yixun Lan wrote:
> > >
> > > Tested-by: Xingyu Chen
> > > Signed-off-by: Yixun Lan
> >
> > Subject is missing "v2" tag and a reference to the previous message:
> > 20171103181703.30434-1-yixun@amlogic.com
>
On Mon, 2017-11-06 at 17:38 +0800, Yixun Lan wrote:
> > >
> > > Tested-by: Xingyu Chen
> > > Signed-off-by: Yixun Lan
> >
> > Subject is missing "v2" tag and a reference to the previous message:
> > 20171103181703.30434-1-yixun@amlogic.com
> >
>
> Ok..
> I was considering this patch as a
Hi Jerome:
On 11/06/17 17:10, Jerome Brunet wrote:
> On Mon, 2017-11-06 at 15:52 +0800, Yixun Lan wrote:
>> According to the datasheet, in Meson-GXBB/GXL series,
>> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
>> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
>>
>> Test
Hi Jerome:
On 11/06/17 17:10, Jerome Brunet wrote:
> On Mon, 2017-11-06 at 15:52 +0800, Yixun Lan wrote:
>> According to the datasheet, in Meson-GXBB/GXL series,
>> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
>> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
>>
>> Test
Hi Neil:
On 11/06/17 16:57, Neil Armstrong wrote:
> On 06/11/2017 08:52, Yixun Lan wrote:
>> According to the datasheet, in Meson-GXBB/GXL series,
>> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
>> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
>>
>> Test passed at gxl_skt
Hi Neil:
On 11/06/17 16:57, Neil Armstrong wrote:
> On 06/11/2017 08:52, Yixun Lan wrote:
>> According to the datasheet, in Meson-GXBB/GXL series,
>> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
>> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
>>
>> Test passed at gxl_skt
On Mon, 2017-11-06 at 15:52 +0800, Yixun Lan wrote:
> According to the datasheet, in Meson-GXBB/GXL series,
> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
>
> Test passed at gxl_skt dev board.
I think this refer to a board
On Mon, 2017-11-06 at 15:52 +0800, Yixun Lan wrote:
> According to the datasheet, in Meson-GXBB/GXL series,
> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
>
> Test passed at gxl_skt dev board.
I think this refer to a board
On 06/11/2017 08:52, Yixun Lan wrote:
> According to the datasheet, in Meson-GXBB/GXL series,
> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
>
> Test passed at gxl_skt dev board.
>
> Tested-by: Xingyu Chen
On 06/11/2017 08:52, Yixun Lan wrote:
> According to the datasheet, in Meson-GXBB/GXL series,
> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
>
> Test passed at gxl_skt dev board.
>
> Tested-by: Xingyu Chen
> Signed-off-by:
According to the datasheet, in Meson-GXBB/GXL series,
The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
Test passed at gxl_skt dev board.
Tested-by: Xingyu Chen
Signed-off-by: Yixun Lan
According to the datasheet, in Meson-GXBB/GXL series,
The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
Test passed at gxl_skt dev board.
Tested-by: Xingyu Chen
Signed-off-by: Yixun Lan
---
I think this error was introduced by a
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