Re: [PATCH] clk: meson: make the spinlock naming more specific

[Kevin Hilman]

Yixun Lan  writes:

> Make the spinlock more specific, so better for lockdep
> debugging and ctags/grep.
>
> Signed-off-by: Yixun Lan 
>
> ---
>
> this patch try to address the issue which bring up by Stephen at [1]
> [1] 
> http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005534.html

FYI... for future reference, it's common to use a Suggested-by tag to
give credit for these kinds of things.  e.g.:

Suggested-by: Stephen Boyd 

Kevin

Re: [PATCH] clk: meson: make the spinlock naming more specific

[Kevin Hilman]

Yixun Lan  writes:

> Make the spinlock more specific, so better for lockdep
> debugging and ctags/grep.
>
> Signed-off-by: Yixun Lan 
>
> ---
>
> this patch try to address the issue which bring up by Stephen at [1]
> [1] 
> http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005534.html

FYI... for future reference, it's common to use a Suggested-by tag to
give credit for these kinds of things.  e.g.:

Suggested-by: Stephen Boyd 

Kevin

[PATCH] clk: meson: make the spinlock naming more specific

[Yixun Lan]

Make the spinlock more specific, so better for lockdep
debugging and ctags/grep.

Signed-off-by: Yixun Lan 

---

this patch try to address the issue which bring up by Stephen at [1]
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005534.html
---
 drivers/clk/meson/axg.c |  34 +++---
 drivers/clk/meson/clkc.h|   2 +-
 drivers/clk/meson/gxbb.c| 112 ++--
 drivers/clk/meson/meson8b.c |  24 +-
 4 files changed, 86 insertions(+), 86 deletions(-)

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 03f57541bc1e..349cbcd299d8 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -19,7 +19,7 @@
 #include "clkc.h"
 #include "axg.h"
 
-static DEFINE_SPINLOCK(clk_lock);
+static DEFINE_SPINLOCK(meson_clk_lock);
 
 static const struct pll_rate_table sys_pll_rate_table[] = {
PLL_RATE(2400, 56, 1, 2),
@@ -129,7 +129,7 @@ static struct meson_clk_pll axg_fixed_pll = {
.shift   = 16,
.width   = 2,
},
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "fixed_pll",
.ops = _clk_pll_ro_ops,
@@ -157,7 +157,7 @@ static struct meson_clk_pll axg_sys_pll = {
},
.rate_table = sys_pll_rate_table,
.rate_count = ARRAY_SIZE(sys_pll_rate_table),
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sys_pll",
.ops = _clk_pll_ro_ops,
@@ -291,7 +291,7 @@ static struct meson_clk_pll axg_gp0_pll = {
},
.rate_table = axg_gp0_pll_rate_table,
.rate_count = ARRAY_SIZE(axg_gp0_pll_rate_table),
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "gp0_pll",
.ops = _clk_pll_ops,
@@ -383,7 +383,7 @@ static struct meson_clk_mpll axg_mpll0 = {
.shift   = 25,
.width   = 1,
},
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll0",
.ops = _clk_mpll_ops,
@@ -413,7 +413,7 @@ static struct meson_clk_mpll axg_mpll1 = {
.shift   = 14,
.width   = 1,
},
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll1",
.ops = _clk_mpll_ops,
@@ -443,7 +443,7 @@ static struct meson_clk_mpll axg_mpll2 = {
.shift   = 14,
.width   = 1,
},
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll2",
.ops = _clk_mpll_ops,
@@ -473,7 +473,7 @@ static struct meson_clk_mpll axg_mpll3 = {
.shift   = 0,
.width   = 1,
},
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll3",
.ops = _clk_mpll_ops,
@@ -499,7 +499,7 @@ static struct clk_mux axg_mpeg_clk_sel = {
.shift = 12,
.flags = CLK_MUX_READ_ONLY,
.table = mux_table_clk81,
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_sel",
.ops = _mux_ro_ops,
@@ -518,7 +518,7 @@ static struct clk_divider axg_mpeg_clk_div = {
.reg = (void *)HHI_MPEG_CLK_CNTL,
.shift = 0,
.width = 7,
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_div",
.ops = _divider_ops,
@@ -531,7 +531,7 @@ static struct clk_divider axg_mpeg_clk_div = {
 static struct clk_gate axg_clk81 = {
.reg = (void *)HHI_MPEG_CLK_CNTL,
.bit_idx = 7,
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "clk81",
.ops = _gate_ops,
@@ -557,7 +557,7 @@ static struct clk_mux axg_sd_emmc_b_clk0_sel = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.mask = 0x7,
.shift = 25,
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_sel",
.ops = _mux_ops,
@@ -571,7 +571,7 @@ static struct clk_divider axg_sd_emmc_b_clk0_div = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.shift = 16,
.width = 7,
-   .lock = _lock,
+   .lock = _clk_lock,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_div",
@@ -585,7 +585,7 @@ static struct clk_divider axg_sd_emmc_b_clk0_div = {
 static struct clk_gate axg_sd_emmc_b_clk0 = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.bit_idx = 23,
-   .lock 

[PATCH] clk: meson: make the spinlock naming more specific

[Yixun Lan]

Make the spinlock more specific, so better for lockdep
debugging and ctags/grep.

Signed-off-by: Yixun Lan 

---

this patch try to address the issue which bring up by Stephen at [1]
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005534.html
---
 drivers/clk/meson/axg.c |  34 +++---
 drivers/clk/meson/clkc.h|   2 +-
 drivers/clk/meson/gxbb.c| 112 ++--
 drivers/clk/meson/meson8b.c |  24 +-
 4 files changed, 86 insertions(+), 86 deletions(-)

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 03f57541bc1e..349cbcd299d8 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -19,7 +19,7 @@
 #include "clkc.h"
 #include "axg.h"
 
-static DEFINE_SPINLOCK(clk_lock);
+static DEFINE_SPINLOCK(meson_clk_lock);
 
 static const struct pll_rate_table sys_pll_rate_table[] = {
PLL_RATE(2400, 56, 1, 2),
@@ -129,7 +129,7 @@ static struct meson_clk_pll axg_fixed_pll = {
.shift   = 16,
.width   = 2,
},
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "fixed_pll",
.ops = _clk_pll_ro_ops,
@@ -157,7 +157,7 @@ static struct meson_clk_pll axg_sys_pll = {
},
.rate_table = sys_pll_rate_table,
.rate_count = ARRAY_SIZE(sys_pll_rate_table),
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sys_pll",
.ops = _clk_pll_ro_ops,
@@ -291,7 +291,7 @@ static struct meson_clk_pll axg_gp0_pll = {
},
.rate_table = axg_gp0_pll_rate_table,
.rate_count = ARRAY_SIZE(axg_gp0_pll_rate_table),
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "gp0_pll",
.ops = _clk_pll_ops,
@@ -383,7 +383,7 @@ static struct meson_clk_mpll axg_mpll0 = {
.shift   = 25,
.width   = 1,
},
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll0",
.ops = _clk_mpll_ops,
@@ -413,7 +413,7 @@ static struct meson_clk_mpll axg_mpll1 = {
.shift   = 14,
.width   = 1,
},
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll1",
.ops = _clk_mpll_ops,
@@ -443,7 +443,7 @@ static struct meson_clk_mpll axg_mpll2 = {
.shift   = 14,
.width   = 1,
},
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll2",
.ops = _clk_mpll_ops,
@@ -473,7 +473,7 @@ static struct meson_clk_mpll axg_mpll3 = {
.shift   = 0,
.width   = 1,
},
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll3",
.ops = _clk_mpll_ops,
@@ -499,7 +499,7 @@ static struct clk_mux axg_mpeg_clk_sel = {
.shift = 12,
.flags = CLK_MUX_READ_ONLY,
.table = mux_table_clk81,
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_sel",
.ops = _mux_ro_ops,
@@ -518,7 +518,7 @@ static struct clk_divider axg_mpeg_clk_div = {
.reg = (void *)HHI_MPEG_CLK_CNTL,
.shift = 0,
.width = 7,
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_div",
.ops = _divider_ops,
@@ -531,7 +531,7 @@ static struct clk_divider axg_mpeg_clk_div = {
 static struct clk_gate axg_clk81 = {
.reg = (void *)HHI_MPEG_CLK_CNTL,
.bit_idx = 7,
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data){
.name = "clk81",
.ops = _gate_ops,
@@ -557,7 +557,7 @@ static struct clk_mux axg_sd_emmc_b_clk0_sel = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.mask = 0x7,
.shift = 25,
-   .lock = _lock,
+   .lock = _clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_sel",
.ops = _mux_ops,
@@ -571,7 +571,7 @@ static struct clk_divider axg_sd_emmc_b_clk0_div = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.shift = 16,
.width = 7,
-   .lock = _lock,
+   .lock = _clk_lock,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_div",
@@ -585,7 +585,7 @@ static struct clk_divider axg_sd_emmc_b_clk0_div = {
 static struct clk_gate axg_sd_emmc_b_clk0 = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.bit_idx = 23,
-   .lock = _lock,
+   .lock