On Fri, 13 Nov 2020 09:27:03 +0100
Fabrice Gasnier wrote:
> On 11/8/20 4:18 PM, Jonathan Cameron wrote:
> > On Fri, 6 Nov 2020 17:57:26 +0100
> > Fabrice Gasnier wrote:
> >
> >> For proper operation, STM32 ADC should be used with a clock duty cycle
> >> of 50%, in the range of 49% to 51%. Dep
On 11/8/20 4:18 PM, Jonathan Cameron wrote:
> On Fri, 6 Nov 2020 17:57:26 +0100
> Fabrice Gasnier wrote:
>
>> For proper operation, STM32 ADC should be used with a clock duty cycle
>> of 50%, in the range of 49% to 51%. Depending on the clock tree, divider
>> can be used in case clock duty cycle
On Fri, 6 Nov 2020 17:57:26 +0100
Fabrice Gasnier wrote:
> For proper operation, STM32 ADC should be used with a clock duty cycle
> of 50%, in the range of 49% to 51%. Depending on the clock tree, divider
> can be used in case clock duty cycle is out of this range.
> In case clk_get_scaled_duty_c
For proper operation, STM32 ADC should be used with a clock duty cycle
of 50%, in the range of 49% to 51%. Depending on the clock tree, divider
can be used in case clock duty cycle is out of this range.
In case clk_get_scaled_duty_cycle() returns an error, kindly apply a
divider by default (don't m
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