On Wed, Mar 06, 2013 at 02:05:52PM +0100, Thomas Gleixner wrote:
> On Wed, 6 Mar 2013, Simon Horman wrote:
>
> > On Wed, Mar 06, 2013 at 11:01:14AM +0100, Thomas Gleixner wrote:
> > > On Wed, 6 Mar 2013, Simon Horman wrote:
> > > > On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
> >
On Wed, Mar 06, 2013 at 02:05:52PM +0100, Thomas Gleixner wrote:
On Wed, 6 Mar 2013, Simon Horman wrote:
On Wed, Mar 06, 2013 at 11:01:14AM +0100, Thomas Gleixner wrote:
On Wed, 6 Mar 2013, Simon Horman wrote:
On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
The SoCs
On Wed, 6 Mar 2013, Simon Horman wrote:
> On Wed, Mar 06, 2013 at 11:01:14AM +0100, Thomas Gleixner wrote:
> > On Wed, 6 Mar 2013, Simon Horman wrote:
> > > On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
> > > > The SoCs using this driver are currently mainly used
> > > > together
On Wed, Mar 06, 2013 at 11:01:14AM +0100, Thomas Gleixner wrote:
> On Wed, 6 Mar 2013, Simon Horman wrote:
> > On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
> > > The SoCs using this driver are currently mainly used
> > > together with regular platform devices so this driver
> > >
On Wed, 6 Mar 2013, Simon Horman wrote:
> On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
> > The SoCs using this driver are currently mainly used
> > together with regular platform devices so this driver
> > allows configuration via platform data to support things
> > like static
On Wed, 6 Mar 2013, Simon Horman wrote:
On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
The SoCs using this driver are currently mainly used
together with regular platform devices so this driver
allows configuration via platform data to support things
like static interrupt
On Wed, Mar 06, 2013 at 11:01:14AM +0100, Thomas Gleixner wrote:
On Wed, 6 Mar 2013, Simon Horman wrote:
On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
The SoCs using this driver are currently mainly used
together with regular platform devices so this driver
allows
On Wed, 6 Mar 2013, Simon Horman wrote:
On Wed, Mar 06, 2013 at 11:01:14AM +0100, Thomas Gleixner wrote:
On Wed, 6 Mar 2013, Simon Horman wrote:
On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
The SoCs using this driver are currently mainly used
together with regular
On Wed, Feb 27, 2013 at 7:28 PM, Paul Mundt wrote:
> On Wed, Feb 27, 2013 at 06:52:51PM +0900, Magnus Damm wrote:
>> As you know, the INTC code that you are referring to is a full
>> interrupt controller designed to work directly with CPU cores like SH
>> and ARM. Newer ARM cores like Cortex-A9
On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
> From: Magnus Damm
>
> This patch adds a driver for external IRQ pins connected
> to the INTC block on recent SoCs from Renesas.
>
> The INTC hardware block usually contains a rather wide
> range of features ranging from external IRQ
On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
From: Magnus Damm d...@opensource.se
This patch adds a driver for external IRQ pins connected
to the INTC block on recent SoCs from Renesas.
The INTC hardware block usually contains a rather wide
range of features ranging from
On Wed, Feb 27, 2013 at 7:28 PM, Paul Mundt let...@linux-sh.org wrote:
On Wed, Feb 27, 2013 at 06:52:51PM +0900, Magnus Damm wrote:
As you know, the INTC code that you are referring to is a full
interrupt controller designed to work directly with CPU cores like SH
and ARM. Newer ARM cores like
On Wed, Feb 27, 2013 at 06:52:51PM +0900, Magnus Damm wrote:
> As you know, the INTC code that you are referring to is a full
> interrupt controller designed to work directly with CPU cores like SH
> and ARM. Newer ARM cores like Cortex-A9 all include the GIC both for
> IPI purpose in case of SMP
On Wed, Feb 27, 2013 at 5:52 PM, Paul Mundt wrote:
> On Wed, Feb 27, 2013 at 05:35:51PM +0900, Magnus Damm wrote:
>> On Wed, Feb 27, 2013 at 5:23 PM, Paul Mundt wrote:
>> > So how exactly does this interact with the existing sh_intc code? Or is
>> > there some reason why you have opted to bypass
On Wed, Feb 27, 2013 at 05:35:51PM +0900, Magnus Damm wrote:
> On Wed, Feb 27, 2013 at 5:23 PM, Paul Mundt wrote:
> > So how exactly does this interact with the existing sh_intc code? Or is
> > there some reason why you have opted to bypass it in order to implement a
> > simplified
On Wed, Feb 27, 2013 at 5:23 PM, Paul Mundt wrote:
> On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
>> From: Magnus Damm
>>
>> This patch adds a driver for external IRQ pins connected
>> to the INTC block on recent SoCs from Renesas.
>>
> So how exactly does this interact with the
On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
> From: Magnus Damm
>
> This patch adds a driver for external IRQ pins connected
> to the INTC block on recent SoCs from Renesas.
>
So how exactly does this interact with the existing sh_intc code? Or is
there some reason why you have
On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
From: Magnus Damm d...@opensource.se
This patch adds a driver for external IRQ pins connected
to the INTC block on recent SoCs from Renesas.
So how exactly does this interact with the existing sh_intc code? Or is
there some reason
On Wed, Feb 27, 2013 at 5:23 PM, Paul Mundt let...@linux-sh.org wrote:
On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
From: Magnus Damm d...@opensource.se
This patch adds a driver for external IRQ pins connected
to the INTC block on recent SoCs from Renesas.
So how exactly
On Wed, Feb 27, 2013 at 05:35:51PM +0900, Magnus Damm wrote:
On Wed, Feb 27, 2013 at 5:23 PM, Paul Mundt let...@linux-sh.org wrote:
So how exactly does this interact with the existing sh_intc code? Or is
there some reason why you have opted to bypass it in order to implement a
simplified
On Wed, Feb 27, 2013 at 5:52 PM, Paul Mundt let...@linux-sh.org wrote:
On Wed, Feb 27, 2013 at 05:35:51PM +0900, Magnus Damm wrote:
On Wed, Feb 27, 2013 at 5:23 PM, Paul Mundt let...@linux-sh.org wrote:
So how exactly does this interact with the existing sh_intc code? Or is
there some reason
On Wed, Feb 27, 2013 at 06:52:51PM +0900, Magnus Damm wrote:
As you know, the INTC code that you are referring to is a full
interrupt controller designed to work directly with CPU cores like SH
and ARM. Newer ARM cores like Cortex-A9 all include the GIC both for
IPI purpose in case of SMP and
On Tue, 19 Feb 2013, Magnus Damm wrote:
> On Tue, Feb 19, 2013 at 7:11 PM, Thomas Gleixner wrote:
> >> +static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
> >
> > Shouldn't the lock be part of struct intc_irqpin_priv ?
>
> Good idea, but I need to lock access to the SENSE
Hi Thomas,
Thanks for your help with the review!
On Tue, Feb 19, 2013 at 7:11 PM, Thomas Gleixner wrote:
> Magnus,
>
> On Mon, 18 Feb 2013, Magnus Damm wrote:
>
>> +static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
>> + int reg)
>>
Hi Morimoto-san,
On Tue, Feb 19, 2013 at 10:04 AM, Kuninori Morimoto
wrote:
>
> Hi Magnus
>
> Thank you for this patch.
> Small comment from me :)
Sure, thanks!
>> +struct intc_irqpin_priv {
>> + struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
>> + struct intc_irqpin_irq
On Tue, Feb 19, 2013 at 10:03 AM, Simon Horman wrote:
> On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
>> From: Magnus Damm
>>
>> This patch adds a driver for external IRQ pins connected
>> to the INTC block on recent SoCs from Renesas.
>>
>> The INTC hardware block usually
Magnus,
On Mon, 18 Feb 2013, Magnus Damm wrote:
> +static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
> + int reg)
> +{
> + struct intc_irqpin_iomem *i = >iomem[reg];
Newline between variable and code please.
> + return
Magnus,
On Mon, 18 Feb 2013, Magnus Damm wrote:
+static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
+ int reg)
+{
+ struct intc_irqpin_iomem *i = p-iomem[reg];
Newline between variable and code please.
+ return
On Tue, Feb 19, 2013 at 10:03 AM, Simon Horman ho...@verge.net.au wrote:
On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
From: Magnus Damm d...@opensource.se
This patch adds a driver for external IRQ pins connected
to the INTC block on recent SoCs from Renesas.
The INTC
Hi Morimoto-san,
On Tue, Feb 19, 2013 at 10:04 AM, Kuninori Morimoto
kuninori.morimoto...@renesas.com wrote:
Hi Magnus
Thank you for this patch.
Small comment from me :)
Sure, thanks!
+struct intc_irqpin_priv {
+ struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
+ struct
Hi Thomas,
Thanks for your help with the review!
On Tue, Feb 19, 2013 at 7:11 PM, Thomas Gleixner t...@linutronix.de wrote:
Magnus,
On Mon, 18 Feb 2013, Magnus Damm wrote:
+static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
+
On Tue, 19 Feb 2013, Magnus Damm wrote:
On Tue, Feb 19, 2013 at 7:11 PM, Thomas Gleixner t...@linutronix.de wrote:
+static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
Shouldn't the lock be part of struct intc_irqpin_priv ?
Good idea, but I need to lock access to
Hi Magnus
Thank you for this patch.
Small comment from me :)
> +struct intc_irqpin_priv {
> + struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
> + struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
> + struct renesas_intc_irqpin_config config;
> + unsigned int number_of_irqs;
> +
On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
> From: Magnus Damm
>
> This patch adds a driver for external IRQ pins connected
> to the INTC block on recent SoCs from Renesas.
>
> The INTC hardware block usually contains a rather wide
> range of features ranging from external IRQ
From: Magnus Damm
This patch adds a driver for external IRQ pins connected
to the INTC block on recent SoCs from Renesas.
The INTC hardware block usually contains a rather wide
range of features ranging from external IRQ pin handling
to legacy interrupt controller support. On older SoCs
the
From: Magnus Damm d...@opensource.se
This patch adds a driver for external IRQ pins connected
to the INTC block on recent SoCs from Renesas.
The INTC hardware block usually contains a rather wide
range of features ranging from external IRQ pin handling
to legacy interrupt controller support. On
On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
From: Magnus Damm d...@opensource.se
This patch adds a driver for external IRQ pins connected
to the INTC block on recent SoCs from Renesas.
The INTC hardware block usually contains a rather wide
range of features ranging from
Hi Magnus
Thank you for this patch.
Small comment from me :)
+struct intc_irqpin_priv {
+ struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
+ struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
+ struct renesas_intc_irqpin_config config;
+ unsigned int number_of_irqs;
+
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