On Mon, Feb 02, 2015 at 09:59:16AM +0100, Paolo Bonzini wrote:
>
>
> On 02/02/2015 08:45, David Gibson wrote:
> > + case H_LOGICAL_CI_LOAD:
> > + ret = kvmppc_h_logical_ci_load(vcpu);
> > + if (ret == H_TOO_HARD) {
> > + printk("Punting
On 02/02/2015 08:45, David Gibson wrote:
> + case H_LOGICAL_CI_LOAD:
> + ret = kvmppc_h_logical_ci_load(vcpu);
> + if (ret == H_TOO_HARD) {
> + printk("Punting H_LOGICAL_CI_LOAD\n");
> + return RESUME_HOST;
> + }
> +
On 02/02/2015 08:45, David Gibson wrote:
+ case H_LOGICAL_CI_LOAD:
+ ret = kvmppc_h_logical_ci_load(vcpu);
+ if (ret == H_TOO_HARD) {
+ printk(Punting H_LOGICAL_CI_LOAD\n);
+ return RESUME_HOST;
+ }
+
On Mon, Feb 02, 2015 at 09:59:16AM +0100, Paolo Bonzini wrote:
On 02/02/2015 08:45, David Gibson wrote:
+ case H_LOGICAL_CI_LOAD:
+ ret = kvmppc_h_logical_ci_load(vcpu);
+ if (ret == H_TOO_HARD) {
+ printk(Punting H_LOGICAL_CI_LOAD\n);
+
On POWER, storage caching is usually configured via the MMU - attributes
such as cache-inhibited are stored in the TLB and the hashed page table.
This makes correctly performing cache inhibited IO accesses awkward when
the MMU is turned off (real mode). Some CPU models provide special
registers
On POWER, storage caching is usually configured via the MMU - attributes
such as cache-inhibited are stored in the TLB and the hashed page table.
This makes correctly performing cache inhibited IO accesses awkward when
the MMU is turned off (real mode). Some CPU models provide special
registers
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