Hugh,
On Thu, Feb 14, 2013 at 09:24:09PM +, Hugh Dickins wrote:
> On Wed, 13 Feb 2013, Andrew Morton wrote:
> > On Wed, 13 Feb 2013 11:39:29 +
> > Catalin Marinas wrote:
> >
> > > ARM processors with LPAE enabled use 3 levels of page tables, with an
> > > entry in the top level (pgd)
Hugh,
On Thu, Feb 14, 2013 at 09:24:09PM +, Hugh Dickins wrote:
On Wed, 13 Feb 2013, Andrew Morton wrote:
On Wed, 13 Feb 2013 11:39:29 +
Catalin Marinas catalin.mari...@arm.com wrote:
ARM processors with LPAE enabled use 3 levels of page tables, with an
entry in the top
On Wed, 13 Feb 2013, Andrew Morton wrote:
> On Wed, 13 Feb 2013 11:39:29 +
> Catalin Marinas wrote:
>
> > ARM processors with LPAE enabled use 3 levels of page tables, with an
> > entry in the top level (pgd) covering 1GB of virtual space. Because of
> > the branch relocation limitations on
On Wed, 13 Feb 2013, Andrew Morton wrote:
On Wed, 13 Feb 2013 11:39:29 +
Catalin Marinas catalin.mari...@arm.com wrote:
ARM processors with LPAE enabled use 3 levels of page tables, with an
entry in the top level (pgd) covering 1GB of virtual space. Because of
the branch relocation
On Wed, 13 Feb 2013 11:39:29 +
Catalin Marinas wrote:
> ARM processors with LPAE enabled use 3 levels of page tables, with an
> entry in the top level (pgd) covering 1GB of virtual space. Because of
> the branch relocation limitations on ARM, the loadable modules are
> mapped 16MB below
ARM processors with LPAE enabled use 3 levels of page tables, with an
entry in the top level (pgd) covering 1GB of virtual space. Because of
the branch relocation limitations on ARM, the loadable modules are
mapped 16MB below PAGE_OFFSET, making the corresponding 1GB pgd shared
between kernel
ARM processors with LPAE enabled use 3 levels of page tables, with an
entry in the top level (pgd) covering 1GB of virtual space. Because of
the branch relocation limitations on ARM, the loadable modules are
mapped 16MB below PAGE_OFFSET, making the corresponding 1GB pgd shared
between kernel
On Wed, 13 Feb 2013 11:39:29 +
Catalin Marinas catalin.mari...@arm.com wrote:
ARM processors with LPAE enabled use 3 levels of page tables, with an
entry in the top level (pgd) covering 1GB of virtual space. Because of
the branch relocation limitations on ARM, the loadable modules are
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