Re: [PATCH] mm: Limit pgd range freeing to mm->task_size

2013-02-18 Thread Catalin Marinas
Hugh, On Thu, Feb 14, 2013 at 09:24:09PM +, Hugh Dickins wrote: > On Wed, 13 Feb 2013, Andrew Morton wrote: > > On Wed, 13 Feb 2013 11:39:29 + > > Catalin Marinas wrote: > > > > > ARM processors with LPAE enabled use 3 levels of page tables, with an > > > entry in the top level (pgd)

Re: [PATCH] mm: Limit pgd range freeing to mm-task_size

2013-02-18 Thread Catalin Marinas
Hugh, On Thu, Feb 14, 2013 at 09:24:09PM +, Hugh Dickins wrote: On Wed, 13 Feb 2013, Andrew Morton wrote: On Wed, 13 Feb 2013 11:39:29 + Catalin Marinas catalin.mari...@arm.com wrote: ARM processors with LPAE enabled use 3 levels of page tables, with an entry in the top

Re: [PATCH] mm: Limit pgd range freeing to mm->task_size

2013-02-14 Thread Hugh Dickins
On Wed, 13 Feb 2013, Andrew Morton wrote: > On Wed, 13 Feb 2013 11:39:29 + > Catalin Marinas wrote: > > > ARM processors with LPAE enabled use 3 levels of page tables, with an > > entry in the top level (pgd) covering 1GB of virtual space. Because of > > the branch relocation limitations on

Re: [PATCH] mm: Limit pgd range freeing to mm-task_size

2013-02-14 Thread Hugh Dickins
On Wed, 13 Feb 2013, Andrew Morton wrote: On Wed, 13 Feb 2013 11:39:29 + Catalin Marinas catalin.mari...@arm.com wrote: ARM processors with LPAE enabled use 3 levels of page tables, with an entry in the top level (pgd) covering 1GB of virtual space. Because of the branch relocation

Re: [PATCH] mm: Limit pgd range freeing to mm->task_size

2013-02-13 Thread Andrew Morton
On Wed, 13 Feb 2013 11:39:29 + Catalin Marinas wrote: > ARM processors with LPAE enabled use 3 levels of page tables, with an > entry in the top level (pgd) covering 1GB of virtual space. Because of > the branch relocation limitations on ARM, the loadable modules are > mapped 16MB below

[PATCH] mm: Limit pgd range freeing to mm->task_size

2013-02-13 Thread Catalin Marinas
ARM processors with LPAE enabled use 3 levels of page tables, with an entry in the top level (pgd) covering 1GB of virtual space. Because of the branch relocation limitations on ARM, the loadable modules are mapped 16MB below PAGE_OFFSET, making the corresponding 1GB pgd shared between kernel

[PATCH] mm: Limit pgd range freeing to mm-task_size

2013-02-13 Thread Catalin Marinas
ARM processors with LPAE enabled use 3 levels of page tables, with an entry in the top level (pgd) covering 1GB of virtual space. Because of the branch relocation limitations on ARM, the loadable modules are mapped 16MB below PAGE_OFFSET, making the corresponding 1GB pgd shared between kernel

Re: [PATCH] mm: Limit pgd range freeing to mm-task_size

2013-02-13 Thread Andrew Morton
On Wed, 13 Feb 2013 11:39:29 + Catalin Marinas catalin.mari...@arm.com wrote: ARM processors with LPAE enabled use 3 levels of page tables, with an entry in the top level (pgd) covering 1GB of virtual space. Because of the branch relocation limitations on ARM, the loadable modules are