On Mon, 17 Aug 2015, Bjorn Helgaas wrote:
On Wed, Jul 29, 2015 at 04:18:53PM -0600, Keith Busch wrote:
The new pcie tuning will check the device's MPS against the parent bridge
when it is initially added to the pci subsystem, prior to attaching
to a driver. If MPS is mismatched, the downstream
On Wed, Jul 29, 2015 at 04:18:53PM -0600, Keith Busch wrote:
> A hot plugged PCI-e device max payload size (MPS) defaults to 0 for
> 128bytes. The device is not usable if the upstream port is configured
> to a higher setting.
>
> Bus configuration was previously done by arch specific and hot plug
On Mon, 17 Aug 2015, Bjorn Helgaas wrote:
On Wed, Jul 29, 2015 at 04:18:53PM -0600, Keith Busch wrote:
The new pcie tuning will check the device's MPS against the parent bridge
when it is initially added to the pci subsystem, prior to attaching
to a driver. If MPS is mismatched, the downstream
On Wed, Jul 29, 2015 at 04:18:53PM -0600, Keith Busch wrote:
A hot plugged PCI-e device max payload size (MPS) defaults to 0 for
128bytes. The device is not usable if the upstream port is configured
to a higher setting.
Bus configuration was previously done by arch specific and hot plug code
A hot plugged PCI-e device max payload size (MPS) defaults to 0 for
128bytes. The device is not usable if the upstream port is configured
to a higher setting.
Bus configuration was previously done by arch specific and hot plug code
after the root port or bridge was scanned, and default behavior
A hot plugged PCI-e device max payload size (MPS) defaults to 0 for
128bytes. The device is not usable if the upstream port is configured
to a higher setting.
Bus configuration was previously done by arch specific and hot plug code
after the root port or bridge was scanned, and default behavior
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