Re: [PATCH] pinctrl/amd: poll InterruptEnable bits in amd_gpio_irq_set_type

2018-09-25 Thread Linus Walleij
On Sat, Sep 22, 2018 at 9:58 PM Daniel Kurtz wrote: > From the AMD BKDG, if WAKE_INT_MASTER_REG.MaskStsEn is set, a software > write to the debounce registers of *any* gpio will block wake/interrupt > status generation for *all* gpios for a length of time that depends on >

Re: [PATCH] pinctrl/amd: poll InterruptEnable bits in amd_gpio_irq_set_type

2018-09-25 Thread Linus Walleij
On Sat, Sep 22, 2018 at 9:58 PM Daniel Kurtz wrote: > From the AMD BKDG, if WAKE_INT_MASTER_REG.MaskStsEn is set, a software > write to the debounce registers of *any* gpio will block wake/interrupt > status generation for *all* gpios for a length of time that depends on >

[PATCH] pinctrl/amd: poll InterruptEnable bits in amd_gpio_irq_set_type

2018-09-22 Thread Daniel Kurtz
>From the AMD BKDG, if WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the debounce registers of *any* gpio will block wake/interrupt status generation for *all* gpios for a length of time that depends on WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the Interrupt Delivery

[PATCH] pinctrl/amd: poll InterruptEnable bits in amd_gpio_irq_set_type

2018-09-22 Thread Daniel Kurtz
>From the AMD BKDG, if WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the debounce registers of *any* gpio will block wake/interrupt status generation for *all* gpios for a length of time that depends on WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the Interrupt Delivery