On Sat, Sep 22, 2018 at 9:58 PM Daniel Kurtz wrote:
> From the AMD BKDG, if WAKE_INT_MASTER_REG.MaskStsEn is set, a software
> write to the debounce registers of *any* gpio will block wake/interrupt
> status generation for *all* gpios for a length of time that depends on
>
On Sat, Sep 22, 2018 at 9:58 PM Daniel Kurtz wrote:
> From the AMD BKDG, if WAKE_INT_MASTER_REG.MaskStsEn is set, a software
> write to the debounce registers of *any* gpio will block wake/interrupt
> status generation for *all* gpios for a length of time that depends on
>
>From the AMD BKDG, if WAKE_INT_MASTER_REG.MaskStsEn is set, a software
write to the debounce registers of *any* gpio will block wake/interrupt
status generation for *all* gpios for a length of time that depends on
WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the Interrupt
Delivery
>From the AMD BKDG, if WAKE_INT_MASTER_REG.MaskStsEn is set, a software
write to the debounce registers of *any* gpio will block wake/interrupt
status generation for *all* gpios for a length of time that depends on
WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the Interrupt
Delivery
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