Re: [discuss] [PATCH] x86_64: fix cpu MHz reporting on constant_tsc cpus
> > Yes. You are right. I will fix that and send a new version. Thanks for > the review. I already fixed it up and fixed some other bugs. The changes to tsc_khz in nmi.c were wrong because the performance counters don't tick at tsc frequency. -Andi - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [discuss] [PATCH] x86_64: fix cpu MHz reporting on constant_tsc cpus
Yes. You are right. I will fix that and send a new version. Thanks for the review. I already fixed it up and fixed some other bugs. The changes to tsc_khz in nmi.c were wrong because the performance counters don't tick at tsc frequency. -Andi - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [discuss] [PATCH] x86_64: fix cpu MHz reporting on constant_tsc cpus
On Thu, Mar 15, 2007 at 12:01:09AM +0100, Andi Kleen wrote:
> On Tuesday 13 March 2007 11:00, Joerg Roedel wrote:
> > From: Mark Langsdorf <[EMAIL PROTECTED]>
> > From: Joerg Roedel <[EMAIL PROTECTED]>
> >
> > This patch fixes the reporting of cpu_mhz in /proc/cpuinfo on CPUs with
> > a constant TSC rate and a kernel with disabled cpufreq.
> >
> > Signed-off-by: Mark Langsdorf <[EMAIL PROTECTED]>
> > Signed-off-by: Joerg Roedel <[EMAIL PROTECTED]>
> >
>
> + cpu_khz = tsc_khz;
> + if (cpu_has(_cpu_data, X86_FEATURE_CONSTANT_TSC) &&
> + nmi_known_cpu()) {
> + cpu_khz = tsc_calibrate_cpu_khz();
> + }
>
>
> I don't think this will do the right thing on Intel CPUs of which
> tsc_calibrate_cpu_khz()
> knows nothing about.
Yes. You are right. I will fix that and send a new version. Thanks for
the review.
Joerg
--
Joerg Roedel
Operating System Research Center
AMD Saxony LLC & Co. KG
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to [EMAIL PROTECTED]
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [discuss] [PATCH] x86_64: fix cpu MHz reporting on constant_tsc cpus
On Thu, Mar 15, 2007 at 12:01:09AM +0100, Andi Kleen wrote:
On Tuesday 13 March 2007 11:00, Joerg Roedel wrote:
From: Mark Langsdorf [EMAIL PROTECTED]
From: Joerg Roedel [EMAIL PROTECTED]
This patch fixes the reporting of cpu_mhz in /proc/cpuinfo on CPUs with
a constant TSC rate and a kernel with disabled cpufreq.
Signed-off-by: Mark Langsdorf [EMAIL PROTECTED]
Signed-off-by: Joerg Roedel [EMAIL PROTECTED]
+ cpu_khz = tsc_khz;
+ if (cpu_has(boot_cpu_data, X86_FEATURE_CONSTANT_TSC)
+ nmi_known_cpu()) {
+ cpu_khz = tsc_calibrate_cpu_khz();
+ }
I don't think this will do the right thing on Intel CPUs of which
tsc_calibrate_cpu_khz()
knows nothing about.
Yes. You are right. I will fix that and send a new version. Thanks for
the review.
Joerg
--
Joerg Roedel
Operating System Research Center
AMD Saxony LLC Co. KG
-
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to [EMAIL PROTECTED]
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [discuss] [PATCH] x86_64: fix cpu MHz reporting on constant_tsc cpus
On Tuesday 13 March 2007 11:00, Joerg Roedel wrote:
> From: Mark Langsdorf <[EMAIL PROTECTED]>
> From: Joerg Roedel <[EMAIL PROTECTED]>
>
> This patch fixes the reporting of cpu_mhz in /proc/cpuinfo on CPUs with
> a constant TSC rate and a kernel with disabled cpufreq.
>
> Signed-off-by: Mark Langsdorf <[EMAIL PROTECTED]>
> Signed-off-by: Joerg Roedel <[EMAIL PROTECTED]>
>
+ cpu_khz = tsc_khz;
+ if (cpu_has(_cpu_data, X86_FEATURE_CONSTANT_TSC) &&
+ nmi_known_cpu()) {
+ cpu_khz = tsc_calibrate_cpu_khz();
+ }
I don't think this will do the right thing on Intel CPUs of which
tsc_calibrate_cpu_khz()
knows nothing about.
-Andi
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to [EMAIL PROTECTED]
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [discuss] [PATCH] x86_64: fix cpu MHz reporting on constant_tsc cpus
On Tuesday 13 March 2007 11:00, Joerg Roedel wrote:
From: Mark Langsdorf [EMAIL PROTECTED]
From: Joerg Roedel [EMAIL PROTECTED]
This patch fixes the reporting of cpu_mhz in /proc/cpuinfo on CPUs with
a constant TSC rate and a kernel with disabled cpufreq.
Signed-off-by: Mark Langsdorf [EMAIL PROTECTED]
Signed-off-by: Joerg Roedel [EMAIL PROTECTED]
+ cpu_khz = tsc_khz;
+ if (cpu_has(boot_cpu_data, X86_FEATURE_CONSTANT_TSC)
+ nmi_known_cpu()) {
+ cpu_khz = tsc_calibrate_cpu_khz();
+ }
I don't think this will do the right thing on Intel CPUs of which
tsc_calibrate_cpu_khz()
knows nothing about.
-Andi
-
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to [EMAIL PROTECTED]
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH] x86_64: fix cpu MHz reporting on constant_tsc cpus
From: Mark Langsdorf <[EMAIL PROTECTED]>
From: Joerg Roedel <[EMAIL PROTECTED]>
This patch fixes the reporting of cpu_mhz in /proc/cpuinfo on CPUs with
a constant TSC rate and a kernel with disabled cpufreq.
Signed-off-by: Mark Langsdorf <[EMAIL PROTECTED]>
Signed-off-by: Joerg Roedel <[EMAIL PROTECTED]>
--
Joerg Roedel
Operating System Research Center
AMD Saxony LLC & Co. KG
diff --git a/arch/x86_64/kernel/apic.c b/arch/x86_64/kernel/apic.c
index 723417d..5f291b2 100644
--- a/arch/x86_64/kernel/apic.c
+++ b/arch/x86_64/kernel/apic.c
@@ -839,7 +839,7 @@ static int __init calibrate_APIC_clock(void)
} while ((tsc - tsc_start) < TICK_COUNT &&
(apic - apic_start) < TICK_COUNT);
- result = (apic_start - apic) * 1000L * cpu_khz /
+ result = (apic_start - apic) * 1000L * tsc_khz /
(tsc - tsc_start);
}
printk("result %d\n", result);
diff --git a/arch/x86_64/kernel/nmi.c b/arch/x86_64/kernel/nmi.c
index 486f4c6..0bbaeda 100644
--- a/arch/x86_64/kernel/nmi.c
+++ b/arch/x86_64/kernel/nmi.c
@@ -168,7 +168,7 @@ void release_evntsel_nmi(unsigned int msr)
clear_bit(counter, &__get_cpu_var(evntsel_nmi_owner));
}
-static __cpuinit inline int nmi_known_cpu(void)
+__cpuinit inline int nmi_known_cpu(void)
{
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_AMD:
@@ -225,8 +225,8 @@ static unsigned int adjust_for_32bit_ctr(unsigned int hz)
* 32nd bit should be 1, for 33.. to be 1.
* Find the appropriate nmi_hz
*/
- if u64)cpu_khz * 1000) / retval) > 0x7fffULL) {
- retval = ((u64)cpu_khz * 1000) / 0x7fffUL + 1;
+ if u64)tsc_khz * 1000) / retval) > 0x7fffULL) {
+ retval = ((u64)tsc_khz * 1000) / 0x7fffUL + 1;
}
return retval;
}
@@ -493,7 +493,7 @@ static int setup_k7_watchdog(void)
/* setup the timer */
wrmsr(evntsel_msr, evntsel, 0);
- wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
+ wrmsrl(perfctr_msr, -((u64)tsc_khz * 1000 / nmi_hz));
apic_write(APIC_LVTPC, APIC_DM_NMI);
evntsel |= K7_EVNTSEL_ENABLE;
wrmsr(evntsel_msr, evntsel, 0);
@@ -601,7 +601,7 @@ static int setup_p4_watchdog(void)
wrmsr(evntsel_msr, evntsel, 0);
wrmsr(cccr_msr, cccr_val, 0);
- wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
+ wrmsrl(perfctr_msr, -((u64)tsc_khz * 1000 / nmi_hz));
apic_write(APIC_LVTPC, APIC_DM_NMI);
cccr_val |= P4_CCCR_ENABLE;
wrmsr(cccr_msr, cccr_val, 0);
@@ -671,7 +671,7 @@ static int setup_intel_arch_watchdog(void)
wrmsr(evntsel_msr, evntsel, 0);
nmi_hz = adjust_for_32bit_ctr(nmi_hz);
- wrmsr(perfctr_msr, (u32)(-((u64)cpu_khz * 1000 / nmi_hz)), 0);
+ wrmsr(perfctr_msr, (u32)(-((u64)tsc_khz * 1000 / nmi_hz)), 0);
apic_write(APIC_LVTPC, APIC_DM_NMI);
evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
@@ -894,7 +894,7 @@ int __kprobes nmi_watchdog_tick(struct pt_regs * regs,
unsigned reason)
apic_write(APIC_LVTPC, APIC_DM_NMI);
/* start the cycle over again */
wrmsrl(wd->perfctr_msr,
- -((u64)cpu_khz * 1000 / nmi_hz));
+ -((u64)tsc_khz * 1000 / nmi_hz));
} else if (wd->perfctr_msr ==
MSR_ARCH_PERFMON_PERFCTR0) {
/*
* ArchPerfom/Core Duo needs to re-unmask
@@ -903,11 +903,11 @@ int __kprobes nmi_watchdog_tick(struct pt_regs * regs,
unsigned reason)
apic_write(APIC_LVTPC, APIC_DM_NMI);
/* ARCH_PERFMON has 32 bit counter writes */
wrmsr(wd->perfctr_msr,
-(u32)(-((u64)cpu_khz * 1000 / nmi_hz)), 0);
+(u32)(-((u64)tsc_khz * 1000 / nmi_hz)), 0);
} else {
/* start the cycle over again */
wrmsrl(wd->perfctr_msr,
- -((u64)cpu_khz * 1000 / nmi_hz));
+ -((u64)tsc_khz * 1000 / nmi_hz));
}
rc = 1;
} else if (nmi_watchdog == NMI_IO_APIC) {
@@ -1003,6 +1003,7 @@ void __trigger_all_cpu_backtrace(void)
}
EXPORT_SYMBOL(nmi_active);
+EXPORT_SYMBOL(nmi_known_cpu);
EXPORT_SYMBOL(nmi_watchdog);
EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c
diff --git a/arch/x86_64/kernel/time.c b/arch/x86_64/kernel/time.c
index 75d73a9..52b5dc1 100644
--- a/arch/x86_64/kernel/time.c
+++
[PATCH] x86_64: fix cpu MHz reporting on constant_tsc cpus
From: Mark Langsdorf [EMAIL PROTECTED]
From: Joerg Roedel [EMAIL PROTECTED]
This patch fixes the reporting of cpu_mhz in /proc/cpuinfo on CPUs with
a constant TSC rate and a kernel with disabled cpufreq.
Signed-off-by: Mark Langsdorf [EMAIL PROTECTED]
Signed-off-by: Joerg Roedel [EMAIL PROTECTED]
--
Joerg Roedel
Operating System Research Center
AMD Saxony LLC Co. KG
diff --git a/arch/x86_64/kernel/apic.c b/arch/x86_64/kernel/apic.c
index 723417d..5f291b2 100644
--- a/arch/x86_64/kernel/apic.c
+++ b/arch/x86_64/kernel/apic.c
@@ -839,7 +839,7 @@ static int __init calibrate_APIC_clock(void)
} while ((tsc - tsc_start) TICK_COUNT
(apic - apic_start) TICK_COUNT);
- result = (apic_start - apic) * 1000L * cpu_khz /
+ result = (apic_start - apic) * 1000L * tsc_khz /
(tsc - tsc_start);
}
printk(result %d\n, result);
diff --git a/arch/x86_64/kernel/nmi.c b/arch/x86_64/kernel/nmi.c
index 486f4c6..0bbaeda 100644
--- a/arch/x86_64/kernel/nmi.c
+++ b/arch/x86_64/kernel/nmi.c
@@ -168,7 +168,7 @@ void release_evntsel_nmi(unsigned int msr)
clear_bit(counter, __get_cpu_var(evntsel_nmi_owner));
}
-static __cpuinit inline int nmi_known_cpu(void)
+__cpuinit inline int nmi_known_cpu(void)
{
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_AMD:
@@ -225,8 +225,8 @@ static unsigned int adjust_for_32bit_ctr(unsigned int hz)
* 32nd bit should be 1, for 33.. to be 1.
* Find the appropriate nmi_hz
*/
- if u64)cpu_khz * 1000) / retval) 0x7fffULL) {
- retval = ((u64)cpu_khz * 1000) / 0x7fffUL + 1;
+ if u64)tsc_khz * 1000) / retval) 0x7fffULL) {
+ retval = ((u64)tsc_khz * 1000) / 0x7fffUL + 1;
}
return retval;
}
@@ -493,7 +493,7 @@ static int setup_k7_watchdog(void)
/* setup the timer */
wrmsr(evntsel_msr, evntsel, 0);
- wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
+ wrmsrl(perfctr_msr, -((u64)tsc_khz * 1000 / nmi_hz));
apic_write(APIC_LVTPC, APIC_DM_NMI);
evntsel |= K7_EVNTSEL_ENABLE;
wrmsr(evntsel_msr, evntsel, 0);
@@ -601,7 +601,7 @@ static int setup_p4_watchdog(void)
wrmsr(evntsel_msr, evntsel, 0);
wrmsr(cccr_msr, cccr_val, 0);
- wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
+ wrmsrl(perfctr_msr, -((u64)tsc_khz * 1000 / nmi_hz));
apic_write(APIC_LVTPC, APIC_DM_NMI);
cccr_val |= P4_CCCR_ENABLE;
wrmsr(cccr_msr, cccr_val, 0);
@@ -671,7 +671,7 @@ static int setup_intel_arch_watchdog(void)
wrmsr(evntsel_msr, evntsel, 0);
nmi_hz = adjust_for_32bit_ctr(nmi_hz);
- wrmsr(perfctr_msr, (u32)(-((u64)cpu_khz * 1000 / nmi_hz)), 0);
+ wrmsr(perfctr_msr, (u32)(-((u64)tsc_khz * 1000 / nmi_hz)), 0);
apic_write(APIC_LVTPC, APIC_DM_NMI);
evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
@@ -894,7 +894,7 @@ int __kprobes nmi_watchdog_tick(struct pt_regs * regs,
unsigned reason)
apic_write(APIC_LVTPC, APIC_DM_NMI);
/* start the cycle over again */
wrmsrl(wd-perfctr_msr,
- -((u64)cpu_khz * 1000 / nmi_hz));
+ -((u64)tsc_khz * 1000 / nmi_hz));
} else if (wd-perfctr_msr ==
MSR_ARCH_PERFMON_PERFCTR0) {
/*
* ArchPerfom/Core Duo needs to re-unmask
@@ -903,11 +903,11 @@ int __kprobes nmi_watchdog_tick(struct pt_regs * regs,
unsigned reason)
apic_write(APIC_LVTPC, APIC_DM_NMI);
/* ARCH_PERFMON has 32 bit counter writes */
wrmsr(wd-perfctr_msr,
-(u32)(-((u64)cpu_khz * 1000 / nmi_hz)), 0);
+(u32)(-((u64)tsc_khz * 1000 / nmi_hz)), 0);
} else {
/* start the cycle over again */
wrmsrl(wd-perfctr_msr,
- -((u64)cpu_khz * 1000 / nmi_hz));
+ -((u64)tsc_khz * 1000 / nmi_hz));
}
rc = 1;
} else if (nmi_watchdog == NMI_IO_APIC) {
@@ -1003,6 +1003,7 @@ void __trigger_all_cpu_backtrace(void)
}
EXPORT_SYMBOL(nmi_active);
+EXPORT_SYMBOL(nmi_known_cpu);
EXPORT_SYMBOL(nmi_watchdog);
EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c
diff --git a/arch/x86_64/kernel/time.c b/arch/x86_64/kernel/time.c
index 75d73a9..52b5dc1 100644
--- a/arch/x86_64/kernel/time.c
+++
