On our hardware, the MACB connected to a heavilly used AXI bus, fails to
correctly write RX descriptors.
This leds to RX ring errors that can be managed.
These patchs add RX error management according to the Cadence MACB User Guide.
The first patch separates the RX and TX rings init in order to
On our hardware, the MACB connected to a heavilly used AXI bus, fails to
correctly write RX descriptors.
This leds to RX ring errors that can be managed.
These patchs add RX error management according to the Cadence MACB User Guide.
The first patch separates the RX and TX rings init in order to
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