Re: [PATCH 0/3] intel-iommu: fix mapping PSI missing for iommu_map()

2018-04-18 Thread Peter Xu
On Wed, Apr 18, 2018 at 12:41:27PM +0800, Peter Xu wrote: > (PSI stands for: Page Selective Invalidations) > > Intel IOMMU has the caching mode to ease emulation of the device. > When that bit is set, we need to send PSIs even for newly mapped > pages. However current driver is not fully obey

Re: [PATCH 0/3] intel-iommu: fix mapping PSI missing for iommu_map()

2018-04-18 Thread Peter Xu
On Wed, Apr 18, 2018 at 12:41:27PM +0800, Peter Xu wrote: > (PSI stands for: Page Selective Invalidations) > > Intel IOMMU has the caching mode to ease emulation of the device. > When that bit is set, we need to send PSIs even for newly mapped > pages. However current driver is not fully obey

Re: [PATCH 0/3] intel-iommu: fix mapping PSI missing for iommu_map()

2018-04-17 Thread Peter Xu
On Wed, Apr 18, 2018 at 12:41:27PM +0800, Peter Xu wrote: > (PSI stands for: Page Selective Invalidations) > > Intel IOMMU has the caching mode to ease emulation of the device. > When that bit is set, we need to send PSIs even for newly mapped > pages. However current driver is not fully obey

Re: [PATCH 0/3] intel-iommu: fix mapping PSI missing for iommu_map()

2018-04-17 Thread Peter Xu
On Wed, Apr 18, 2018 at 12:41:27PM +0800, Peter Xu wrote: > (PSI stands for: Page Selective Invalidations) > > Intel IOMMU has the caching mode to ease emulation of the device. > When that bit is set, we need to send PSIs even for newly mapped > pages. However current driver is not fully obey

[PATCH 0/3] intel-iommu: fix mapping PSI missing for iommu_map()

2018-04-17 Thread Peter Xu
(PSI stands for: Page Selective Invalidations) Intel IOMMU has the caching mode to ease emulation of the device. When that bit is set, we need to send PSIs even for newly mapped pages. However current driver is not fully obey the rule. E.g., iommu_map() API will only do the mapping but it never

[PATCH 0/3] intel-iommu: fix mapping PSI missing for iommu_map()

2018-04-17 Thread Peter Xu
(PSI stands for: Page Selective Invalidations) Intel IOMMU has the caching mode to ease emulation of the device. When that bit is set, we need to send PSIs even for newly mapped pages. However current driver is not fully obey the rule. E.g., iommu_map() API will only do the mapping but it never