Hello,
On Wed, Sep 04, 2013 at 10:06:23AM +0200, Alexander Gordeev wrote:
> > Please separate out threaded IRQ support from multiple MSI.
>
> This series does not really bring any structural change to the AHCI code -
> just tweaks the MSI initialization.
>
> As threaded IRQ support vs multiple M
Hello,
On Wed, Sep 04, 2013 at 02:32:39PM +0200, Alexander Gordeev wrote:
> Hmm.. that is actually a great idea. What I am not sure about whether is
> a dummy port still can send (spurious?) interrupts? The hardware interrupt
> handler would have to be reworked then. Seems as a yet another topic t
On Tue, Sep 03, 2013 at 10:09:54AM -0400, Tejun Heo wrote:
> On Tue, Sep 03, 2013 at 09:55:41AM -0400, Tejun Heo wrote:
> > Hmmm I've been looking at the code and and a curiosity. Why does
> > multiple MSI support implicitly enabled threaded IRQ handling? Why
> > are those two linked? Also,
On Tue, Sep 03, 2013 at 12:24:11PM -0400, Tejun Heo wrote:
> Hello,
>
> On Tue, Sep 03, 2013 at 04:57:19PM +0200, Alexander Gordeev wrote:
> > Multiple MSI support enables threaded IRQ handling, because at the time of
> > posting I did not want to intrude into the existing single-MSI codebase
> >
Hello,
On Tue, Sep 03, 2013 at 04:57:19PM +0200, Alexander Gordeev wrote:
> Multiple MSI support enables threaded IRQ handling, because at the time of
> posting I did not want to intrude into the existing single-MSI codebase while
> multiple MSI/multipe CPU approach gained good numbers (below).
P
On Tue, Sep 03, 2013 at 09:55:41AM -0400, Tejun Heo wrote:
> Hello,
>
> On Mon, Sep 02, 2013 at 10:59:07AM +0200, Alexander Gordeev wrote:
> > This series is aimed to conserve on othewise wasted interrupt
> > resources for 10 of 16 unused MSI vectors for AHCI devices on
> > Intel chipsets.
>
> Hm
On Tue, Sep 03, 2013 at 09:55:41AM -0400, Tejun Heo wrote:
> Hmmm I've been looking at the code and and a curiosity. Why does
> multiple MSI support implicitly enabled threaded IRQ handling? Why
> are those two linked? Also, do you have any numbers to show that this
> actually is better? Ha
Hello,
On Mon, Sep 02, 2013 at 10:59:07AM +0200, Alexander Gordeev wrote:
> This series is aimed to conserve on othewise wasted interrupt
> resources for 10 of 16 unused MSI vectors for AHCI devices on
> Intel chipsets.
Hmmm I've been looking at the code and and a curiosity. Why does
multipl
This series is aimed to conserve on othewise wasted interrupt
resources for 10 of 16 unused MSI vectors for AHCI devices on
Intel chipsets.
Alexander Gordeev (4):
PCI/MSI: Introduce pci_enable_msi_block_part() interface
MSI/x86: Support pci_enable_msi_block_part() interface
AHCI: Conserve in
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