Re: [PATCH 0/6] crypto: SHA512 multibuffer implementation

On Mon, Jun 27, 2016 at 10:20:03AM -0700, Megha Dey wrote: > From: Megha Dey > > In this patch series, we introduce the multi-buffer crypto algorithm on > x86_64 and apply it to SHA512 hash computation. The multi-buffer technique > takes advantage of the 8 data lanes

Re: [PATCH 0/6] crypto: SHA512 multibuffer implementation

On Mon, Jun 27, 2016 at 10:20:03AM -0700, Megha Dey wrote: > From: Megha Dey > > In this patch series, we introduce the multi-buffer crypto algorithm on > x86_64 and apply it to SHA512 hash computation. The multi-buffer technique > takes advantage of the 8 data lanes in the AVX2 registers and

[PATCH 0/6] crypto: SHA512 multibuffer implementation

From: Megha Dey In this patch series, we introduce the multi-buffer crypto algorithm on x86_64 and apply it to SHA512 hash computation. The multi-buffer technique takes advantage of the 8 data lanes in the AVX2 registers and allows computation to be performed on data

[PATCH 0/6] crypto: SHA512 multibuffer implementation

From: Megha Dey In this patch series, we introduce the multi-buffer crypto algorithm on x86_64 and apply it to SHA512 hash computation. The multi-buffer technique takes advantage of the 8 data lanes in the AVX2 registers and allows computation to be performed on data from multiple jobs in

[PATCH 0/6] crypto: SHA512 multibuffer implementation

From: Megha Dey In this patch series, we introduce the multi-buffer crypto algorithm on x86_64 and apply it to SHA512 hash computation. The multi-buffer technique takes advantage of the 8 data lanes in the AVX2 registers and allows computation to be performed on data

[PATCH 0/6] crypto: SHA512 multibuffer implementation

From: Megha Dey In this patch series, we introduce the multi-buffer crypto algorithm on x86_64 and apply it to SHA512 hash computation. The multi-buffer technique takes advantage of the 8 data lanes in the AVX2 registers and allows computation to be performed on data from multiple jobs in