RE: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
Hi Rob,
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Wednesday, December 05, 2018 2:21 PM
> To: Jolly Shah
> Cc: mark.rutl...@arm.com; devicet...@vger.kernel.org; Nava kishore Manne
> ; linux-kernel@vger.kernel.org; Rajan Vaja
> ; Michal Simek ; linux-arm-
> ker...@lists.infradead.org
> Subject: Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
>
> On Wed, Dec 05, 2018 at 08:29:36PM +, Jolly Shah wrote:
> > Hi Rob,
> >
> > Thanks for the review. Please find my responses inline.
>
> You need to fix your mail client to wrap lines.
Thanks I will.
>
> > Thanks,
> > Jolly Shah
> >
> > > -Original Message-
> > > From: Rob Herring [mailto:r...@kernel.org]
> > > Sent: Tuesday, December 04, 2018 2:06 PM
> > > To: Jolly Shah
> > > Cc: mark.rutl...@arm.com; Michal Simek ; Rajan Vaja
> > > ; Nava kishore Manne ; linux-
> arm-
> > > ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> > > devicet...@vger.kernel.org; Jolly Shah
> > > Subject: Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP
> core
> > >
> > > On Fri, Nov 16, 2018 at 03:56:50PM -0800, Jolly Shah wrote:
> > > > Base firmware node and clock child node binding are part of mainline
> kernel.
> > > This patchset adds documentation to describe rest of the firmware child
> node
> > > bindings.
> > > > Complete firmware DT node example is shown below for ease of
> > > understanding:
> > >
> > > Shouldn't there be a fpga mgr node too? Called pcap IIRC.
> > >
> > [Jolly] As you suggested, we only added child nodes if the
> > sub-functions have their own resources (clks, irqs, etc.). FPGA doesn't
> > have any resources so not added . Firmware driver would still register
> > it as mfd device to instantiate the driver.
>
> Okay, but won't their need to be child devices for
There are no fpga child devices. Should it be moved out?
>
>
> >
> > > >
> > > > firmware {
> > > > zynqmp_firmware: zynqmp-firmware {
> > > > compatible = "xlnx,zynqmp-firmware";
> > > > method = "smc";
> > > > #power-domain-cells = <1>;
> > > > #reset-cells = <1>;
> > > >
> > > > zynqmp_clk: clock-controller {
> > > > #clock-cells = <1>;
> > > > compatible = "xlnx,zynqmp-clk";
> > > > clocks = <_ref_clk>, <_clk>,
> > > <_alt_ref_clk>, <_ref_clk>, <_crx_ref_clk>;
> > > > clock-names = "pss_ref_clk", "video_clk",
> > > "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
> > > > };
> > > >
> > > > zynqmp_power: zynqmp-power {
> > > > compatible = "xlnx,zynqmp-power";
> > > > interrupts = <0 35 4>;
> > > > };
> > > >
> > > > nvmem_firmware {
> > > > compatible = "xlnx,zynqmp-nvmem-fw";
> > > > #address-cells = <1>;
> > > > #size-cells = <1>;
> > > >
> > > > /* Data cells */
> > > > soc_revision: soc_revision {
> > > > reg = <0x0 0x4>;
> > > > };
> > > > };
> > > >
> > > > afi0: afi0 {
> > > > compatible = "xlnx,afi-fpga";
> > > > config-afi = <0 2>, <1 1>, <2 1>;
> > > > };
> > > >
> > > > qspi: spi@ff0f {
> > >
> > > Why is this under firmware node?
> > [Jolly] Qspi is a user of eemi API provided by firmware node to
> > perform privileged register writes. Alternatively, we can keep such
> > user nodes outside of firmware node and keep nodes which firmware is
> > provider for like clock, reset, pins and power.
> > Please suggest.
>
> Child nodes of the firmware should be providers, not consumers (of the
&
RE: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
Hi Rob,
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Wednesday, December 05, 2018 2:21 PM
> To: Jolly Shah
> Cc: mark.rutl...@arm.com; devicet...@vger.kernel.org; Nava kishore Manne
> ; linux-kernel@vger.kernel.org; Rajan Vaja
> ; Michal Simek ; linux-arm-
> ker...@lists.infradead.org
> Subject: Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
>
> On Wed, Dec 05, 2018 at 08:29:36PM +, Jolly Shah wrote:
> > Hi Rob,
> >
> > Thanks for the review. Please find my responses inline.
>
> You need to fix your mail client to wrap lines.
Thanks I will.
>
> > Thanks,
> > Jolly Shah
> >
> > > -Original Message-
> > > From: Rob Herring [mailto:r...@kernel.org]
> > > Sent: Tuesday, December 04, 2018 2:06 PM
> > > To: Jolly Shah
> > > Cc: mark.rutl...@arm.com; Michal Simek ; Rajan Vaja
> > > ; Nava kishore Manne ; linux-
> arm-
> > > ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> > > devicet...@vger.kernel.org; Jolly Shah
> > > Subject: Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP
> core
> > >
> > > On Fri, Nov 16, 2018 at 03:56:50PM -0800, Jolly Shah wrote:
> > > > Base firmware node and clock child node binding are part of mainline
> kernel.
> > > This patchset adds documentation to describe rest of the firmware child
> node
> > > bindings.
> > > > Complete firmware DT node example is shown below for ease of
> > > understanding:
> > >
> > > Shouldn't there be a fpga mgr node too? Called pcap IIRC.
> > >
> > [Jolly] As you suggested, we only added child nodes if the
> > sub-functions have their own resources (clks, irqs, etc.). FPGA doesn't
> > have any resources so not added . Firmware driver would still register
> > it as mfd device to instantiate the driver.
>
> Okay, but won't their need to be child devices for
There are no fpga child devices. Should it be moved out?
>
>
> >
> > > >
> > > > firmware {
> > > > zynqmp_firmware: zynqmp-firmware {
> > > > compatible = "xlnx,zynqmp-firmware";
> > > > method = "smc";
> > > > #power-domain-cells = <1>;
> > > > #reset-cells = <1>;
> > > >
> > > > zynqmp_clk: clock-controller {
> > > > #clock-cells = <1>;
> > > > compatible = "xlnx,zynqmp-clk";
> > > > clocks = <_ref_clk>, <_clk>,
> > > <_alt_ref_clk>, <_ref_clk>, <_crx_ref_clk>;
> > > > clock-names = "pss_ref_clk", "video_clk",
> > > "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
> > > > };
> > > >
> > > > zynqmp_power: zynqmp-power {
> > > > compatible = "xlnx,zynqmp-power";
> > > > interrupts = <0 35 4>;
> > > > };
> > > >
> > > > nvmem_firmware {
> > > > compatible = "xlnx,zynqmp-nvmem-fw";
> > > > #address-cells = <1>;
> > > > #size-cells = <1>;
> > > >
> > > > /* Data cells */
> > > > soc_revision: soc_revision {
> > > > reg = <0x0 0x4>;
> > > > };
> > > > };
> > > >
> > > > afi0: afi0 {
> > > > compatible = "xlnx,afi-fpga";
> > > > config-afi = <0 2>, <1 1>, <2 1>;
> > > > };
> > > >
> > > > qspi: spi@ff0f {
> > >
> > > Why is this under firmware node?
> > [Jolly] Qspi is a user of eemi API provided by firmware node to
> > perform privileged register writes. Alternatively, we can keep such
> > user nodes outside of firmware node and keep nodes which firmware is
> > provider for like clock, reset, pins and power.
> > Please suggest.
>
> Child nodes of the firmware should be providers, not consumers (of the
&
Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
On Wed, Dec 05, 2018 at 08:29:36PM +, Jolly Shah wrote:
> Hi Rob,
>
> Thanks for the review. Please find my responses inline.
You need to fix your mail client to wrap lines.
> Thanks,
> Jolly Shah
>
> > -Original Message-
> > From: Rob Herring [mailto:r...@kernel.org]
> > Sent: Tuesday, December 04, 2018 2:06 PM
> > To: Jolly Shah
> > Cc: mark.rutl...@arm.com; Michal Simek ; Rajan Vaja
> > ; Nava kishore Manne ; linux-arm-
> > ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> > devicet...@vger.kernel.org; Jolly Shah
> > Subject: Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
> >
> > On Fri, Nov 16, 2018 at 03:56:50PM -0800, Jolly Shah wrote:
> > > Base firmware node and clock child node binding are part of mainline
> > > kernel.
> > This patchset adds documentation to describe rest of the firmware child node
> > bindings.
> > > Complete firmware DT node example is shown below for ease of
> > understanding:
> >
> > Shouldn't there be a fpga mgr node too? Called pcap IIRC.
> >
> [Jolly] As you suggested, we only added child nodes if the
> sub-functions have their own resources (clks, irqs, etc.). FPGA doesn't
> have any resources so not added . Firmware driver would still register
> it as mfd device to instantiate the driver.
Okay, but won't their need to be child devices for
>
> > >
> > > firmware {
> > > zynqmp_firmware: zynqmp-firmware {
> > > compatible = "xlnx,zynqmp-firmware";
> > > method = "smc";
> > > #power-domain-cells = <1>;
> > > #reset-cells = <1>;
> > >
> > > zynqmp_clk: clock-controller {
> > > #clock-cells = <1>;
> > > compatible = "xlnx,zynqmp-clk";
> > > clocks = <_ref_clk>, <_clk>,
> > <_alt_ref_clk>, <_ref_clk>, <_crx_ref_clk>;
> > > clock-names = "pss_ref_clk", "video_clk",
> > "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
> > > };
> > >
> > > zynqmp_power: zynqmp-power {
> > > compatible = "xlnx,zynqmp-power";
> > > interrupts = <0 35 4>;
> > > };
> > >
> > > nvmem_firmware {
> > > compatible = "xlnx,zynqmp-nvmem-fw";
> > > #address-cells = <1>;
> > > #size-cells = <1>;
> > >
> > > /* Data cells */
> > > soc_revision: soc_revision {
> > > reg = <0x0 0x4>;
> > > };
> > > };
> > >
> > > afi0: afi0 {
> > > compatible = "xlnx,afi-fpga";
> > > config-afi = <0 2>, <1 1>, <2 1>;
> > > };
> > >
> > > qspi: spi@ff0f {
> >
> > Why is this under firmware node?
> [Jolly] Qspi is a user of eemi API provided by firmware node to
> perform privileged register writes. Alternatively, we can keep such
> user nodes outside of firmware node and keep nodes which firmware is
> provider for like clock, reset, pins and power.
> Please suggest.
Child nodes of the firmware should be providers, not consumers (of the
firmware). If you had a firmware interface to that provided a SPI
interface, then it would be here. But just having a special mechanism to
access the registers.
> >
> > > compatible = "xlnx,zynqmp-qspi-1.0";
If this same block works with unprivileged accesses, then you will need
some way to distinguish that.
> > > clock-names = "ref_clk", "pclk";
> > > clocks = <_clk _clk>;
> > > interrupts = <0 15 4>;
> > > interrupt-parent = <>;
> > > num-cs = <1>;
> > > reg = <0x0 0xff0f 0x1000>,<0x0 0xc000
> > 0x800>;
> > > };
> > >
> > > serdes: zynqmp_phy@fd40 {
> >
> > And this?
>
> [Jolly] Same as above.
>
> >
> > > compatible = "xlnx,zynqmp-psgtr";
> > > status = "okay";
>
Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
On Wed, Dec 05, 2018 at 08:29:36PM +, Jolly Shah wrote:
> Hi Rob,
>
> Thanks for the review. Please find my responses inline.
You need to fix your mail client to wrap lines.
> Thanks,
> Jolly Shah
>
> > -Original Message-
> > From: Rob Herring [mailto:r...@kernel.org]
> > Sent: Tuesday, December 04, 2018 2:06 PM
> > To: Jolly Shah
> > Cc: mark.rutl...@arm.com; Michal Simek ; Rajan Vaja
> > ; Nava kishore Manne ; linux-arm-
> > ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> > devicet...@vger.kernel.org; Jolly Shah
> > Subject: Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
> >
> > On Fri, Nov 16, 2018 at 03:56:50PM -0800, Jolly Shah wrote:
> > > Base firmware node and clock child node binding are part of mainline
> > > kernel.
> > This patchset adds documentation to describe rest of the firmware child node
> > bindings.
> > > Complete firmware DT node example is shown below for ease of
> > understanding:
> >
> > Shouldn't there be a fpga mgr node too? Called pcap IIRC.
> >
> [Jolly] As you suggested, we only added child nodes if the
> sub-functions have their own resources (clks, irqs, etc.). FPGA doesn't
> have any resources so not added . Firmware driver would still register
> it as mfd device to instantiate the driver.
Okay, but won't their need to be child devices for
>
> > >
> > > firmware {
> > > zynqmp_firmware: zynqmp-firmware {
> > > compatible = "xlnx,zynqmp-firmware";
> > > method = "smc";
> > > #power-domain-cells = <1>;
> > > #reset-cells = <1>;
> > >
> > > zynqmp_clk: clock-controller {
> > > #clock-cells = <1>;
> > > compatible = "xlnx,zynqmp-clk";
> > > clocks = <_ref_clk>, <_clk>,
> > <_alt_ref_clk>, <_ref_clk>, <_crx_ref_clk>;
> > > clock-names = "pss_ref_clk", "video_clk",
> > "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
> > > };
> > >
> > > zynqmp_power: zynqmp-power {
> > > compatible = "xlnx,zynqmp-power";
> > > interrupts = <0 35 4>;
> > > };
> > >
> > > nvmem_firmware {
> > > compatible = "xlnx,zynqmp-nvmem-fw";
> > > #address-cells = <1>;
> > > #size-cells = <1>;
> > >
> > > /* Data cells */
> > > soc_revision: soc_revision {
> > > reg = <0x0 0x4>;
> > > };
> > > };
> > >
> > > afi0: afi0 {
> > > compatible = "xlnx,afi-fpga";
> > > config-afi = <0 2>, <1 1>, <2 1>;
> > > };
> > >
> > > qspi: spi@ff0f {
> >
> > Why is this under firmware node?
> [Jolly] Qspi is a user of eemi API provided by firmware node to
> perform privileged register writes. Alternatively, we can keep such
> user nodes outside of firmware node and keep nodes which firmware is
> provider for like clock, reset, pins and power.
> Please suggest.
Child nodes of the firmware should be providers, not consumers (of the
firmware). If you had a firmware interface to that provided a SPI
interface, then it would be here. But just having a special mechanism to
access the registers.
> >
> > > compatible = "xlnx,zynqmp-qspi-1.0";
If this same block works with unprivileged accesses, then you will need
some way to distinguish that.
> > > clock-names = "ref_clk", "pclk";
> > > clocks = <_clk _clk>;
> > > interrupts = <0 15 4>;
> > > interrupt-parent = <>;
> > > num-cs = <1>;
> > > reg = <0x0 0xff0f 0x1000>,<0x0 0xc000
> > 0x800>;
> > > };
> > >
> > > serdes: zynqmp_phy@fd40 {
> >
> > And this?
>
> [Jolly] Same as above.
>
> >
> > > compatible = "xlnx,zynqmp-psgtr";
> > > status = "okay";
>
RE: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
Hi Rob,
Thanks for the review. Please find my responses inline.
Thanks,
Jolly Shah
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Tuesday, December 04, 2018 2:06 PM
> To: Jolly Shah
> Cc: mark.rutl...@arm.com; Michal Simek ; Rajan Vaja
> ; Nava kishore Manne ; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicet...@vger.kernel.org; Jolly Shah
> Subject: Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
>
> On Fri, Nov 16, 2018 at 03:56:50PM -0800, Jolly Shah wrote:
> > Base firmware node and clock child node binding are part of mainline kernel.
> This patchset adds documentation to describe rest of the firmware child node
> bindings.
> > Complete firmware DT node example is shown below for ease of
> understanding:
>
> Shouldn't there be a fpga mgr node too? Called pcap IIRC.
>
[Jolly] As you suggested, we only added child nodes if the sub-functions have
their own resources (clks, irqs, etc.). FPGA doesn't have any resources so not
added . Firmware driver would still register it as mfd device to instantiate
the driver.
> >
> > firmware {
> > zynqmp_firmware: zynqmp-firmware {
> > compatible = "xlnx,zynqmp-firmware";
> > method = "smc";
> > #power-domain-cells = <1>;
> > #reset-cells = <1>;
> >
> > zynqmp_clk: clock-controller {
> > #clock-cells = <1>;
> > compatible = "xlnx,zynqmp-clk";
> > clocks = <_ref_clk>, <_clk>,
> <_alt_ref_clk>, <_ref_clk>, <_crx_ref_clk>;
> > clock-names = "pss_ref_clk", "video_clk",
> "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
> > };
> >
> > zynqmp_power: zynqmp-power {
> > compatible = "xlnx,zynqmp-power";
> > interrupts = <0 35 4>;
> > };
> >
> > nvmem_firmware {
> > compatible = "xlnx,zynqmp-nvmem-fw";
> > #address-cells = <1>;
> > #size-cells = <1>;
> >
> > /* Data cells */
> > soc_revision: soc_revision {
> > reg = <0x0 0x4>;
> > };
> > };
> >
> > afi0: afi0 {
> > compatible = "xlnx,afi-fpga";
> > config-afi = <0 2>, <1 1>, <2 1>;
> > };
> >
> > qspi: spi@ff0f {
>
> Why is this under firmware node?
[Jolly] Qspi is a user of eemi API provided by firmware node to perform
privileged register writes. Alternatively, we can keep such user nodes outside
of firmware node and keep nodes which firmware is provider for like clock,
reset, pins and power.
Please suggest.
>
> > compatible = "xlnx,zynqmp-qspi-1.0";
> > clock-names = "ref_clk", "pclk";
> > clocks = <_clk _clk>;
> > interrupts = <0 15 4>;
> > interrupt-parent = <>;
> > num-cs = <1>;
> > reg = <0x0 0xff0f 0x1000>,<0x0 0xc000
> 0x800>;
> > };
> >
> > serdes: zynqmp_phy@fd40 {
>
> And this?
[Jolly] Same as above.
>
> > compatible = "xlnx,zynqmp-psgtr";
> > status = "okay";
> > reg = <0x0 0xfd40 0x0 0x4>, <0x0 0xfd3d
> 0x0 0x1000>,
> > <0x0 0xff5e 0x0 0x1000>;
> > reg-names = "serdes", "siou", "lpd";
> >
> > lane0: lane@0 {
> > #phy-cells = <4>;
> > };
> > lane1: lane@1 {
> > #phy-cells = <4>;
> > };
> > lane2: lane@2 {
> > #phy-cells = <4>;
> > };
> > lane3: lane@3 {
> > #phy-cells = <4>;
> > };
> > };
> >
> > pinctrl_ua
RE: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
Hi Rob,
Thanks for the review. Please find my responses inline.
Thanks,
Jolly Shah
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Tuesday, December 04, 2018 2:06 PM
> To: Jolly Shah
> Cc: mark.rutl...@arm.com; Michal Simek ; Rajan Vaja
> ; Nava kishore Manne ; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicet...@vger.kernel.org; Jolly Shah
> Subject: Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
>
> On Fri, Nov 16, 2018 at 03:56:50PM -0800, Jolly Shah wrote:
> > Base firmware node and clock child node binding are part of mainline kernel.
> This patchset adds documentation to describe rest of the firmware child node
> bindings.
> > Complete firmware DT node example is shown below for ease of
> understanding:
>
> Shouldn't there be a fpga mgr node too? Called pcap IIRC.
>
[Jolly] As you suggested, we only added child nodes if the sub-functions have
their own resources (clks, irqs, etc.). FPGA doesn't have any resources so not
added . Firmware driver would still register it as mfd device to instantiate
the driver.
> >
> > firmware {
> > zynqmp_firmware: zynqmp-firmware {
> > compatible = "xlnx,zynqmp-firmware";
> > method = "smc";
> > #power-domain-cells = <1>;
> > #reset-cells = <1>;
> >
> > zynqmp_clk: clock-controller {
> > #clock-cells = <1>;
> > compatible = "xlnx,zynqmp-clk";
> > clocks = <_ref_clk>, <_clk>,
> <_alt_ref_clk>, <_ref_clk>, <_crx_ref_clk>;
> > clock-names = "pss_ref_clk", "video_clk",
> "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
> > };
> >
> > zynqmp_power: zynqmp-power {
> > compatible = "xlnx,zynqmp-power";
> > interrupts = <0 35 4>;
> > };
> >
> > nvmem_firmware {
> > compatible = "xlnx,zynqmp-nvmem-fw";
> > #address-cells = <1>;
> > #size-cells = <1>;
> >
> > /* Data cells */
> > soc_revision: soc_revision {
> > reg = <0x0 0x4>;
> > };
> > };
> >
> > afi0: afi0 {
> > compatible = "xlnx,afi-fpga";
> > config-afi = <0 2>, <1 1>, <2 1>;
> > };
> >
> > qspi: spi@ff0f {
>
> Why is this under firmware node?
[Jolly] Qspi is a user of eemi API provided by firmware node to perform
privileged register writes. Alternatively, we can keep such user nodes outside
of firmware node and keep nodes which firmware is provider for like clock,
reset, pins and power.
Please suggest.
>
> > compatible = "xlnx,zynqmp-qspi-1.0";
> > clock-names = "ref_clk", "pclk";
> > clocks = <_clk _clk>;
> > interrupts = <0 15 4>;
> > interrupt-parent = <>;
> > num-cs = <1>;
> > reg = <0x0 0xff0f 0x1000>,<0x0 0xc000
> 0x800>;
> > };
> >
> > serdes: zynqmp_phy@fd40 {
>
> And this?
[Jolly] Same as above.
>
> > compatible = "xlnx,zynqmp-psgtr";
> > status = "okay";
> > reg = <0x0 0xfd40 0x0 0x4>, <0x0 0xfd3d
> 0x0 0x1000>,
> > <0x0 0xff5e 0x0 0x1000>;
> > reg-names = "serdes", "siou", "lpd";
> >
> > lane0: lane@0 {
> > #phy-cells = <4>;
> > };
> > lane1: lane@1 {
> > #phy-cells = <4>;
> > };
> > lane2: lane@2 {
> > #phy-cells = <4>;
> > };
> > lane3: lane@3 {
> > #phy-cells = <4>;
> > };
> > };
> >
> > pinctrl_ua
Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
On Fri, Nov 16, 2018 at 03:56:50PM -0800, Jolly Shah wrote:
> Base firmware node and clock child node binding are part of mainline kernel.
> This patchset adds documentation to describe rest of the firmware child node
> bindings.
> Complete firmware DT node example is shown below for ease of understanding:
Shouldn't there be a fpga mgr node too? Called pcap IIRC.
>
> firmware {
> zynqmp_firmware: zynqmp-firmware {
> compatible = "xlnx,zynqmp-firmware";
> method = "smc";
> #power-domain-cells = <1>;
> #reset-cells = <1>;
>
> zynqmp_clk: clock-controller {
> #clock-cells = <1>;
> compatible = "xlnx,zynqmp-clk";
> clocks = <_ref_clk>, <_clk>,
> <_alt_ref_clk>, <_ref_clk>, <_crx_ref_clk>;
> clock-names = "pss_ref_clk", "video_clk",
> "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
> };
>
> zynqmp_power: zynqmp-power {
> compatible = "xlnx,zynqmp-power";
> interrupts = <0 35 4>;
> };
>
> nvmem_firmware {
> compatible = "xlnx,zynqmp-nvmem-fw";
> #address-cells = <1>;
> #size-cells = <1>;
>
> /* Data cells */
> soc_revision: soc_revision {
> reg = <0x0 0x4>;
> };
> };
>
> afi0: afi0 {
> compatible = "xlnx,afi-fpga";
> config-afi = <0 2>, <1 1>, <2 1>;
> };
>
> qspi: spi@ff0f {
Why is this under firmware node?
> compatible = "xlnx,zynqmp-qspi-1.0";
> clock-names = "ref_clk", "pclk";
> clocks = <_clk _clk>;
> interrupts = <0 15 4>;
> interrupt-parent = <>;
> num-cs = <1>;
> reg = <0x0 0xff0f 0x1000>,<0x0 0xc000
> 0x800>;
> };
>
> serdes: zynqmp_phy@fd40 {
And this?
> compatible = "xlnx,zynqmp-psgtr";
> status = "okay";
> reg = <0x0 0xfd40 0x0 0x4>, <0x0 0xfd3d 0x0
> 0x1000>,
> <0x0 0xff5e 0x0 0x1000>;
> reg-names = "serdes", "siou", "lpd";
>
> lane0: lane@0 {
> #phy-cells = <4>;
> };
> lane1: lane@1 {
> #phy-cells = <4>;
> };
> lane2: lane@2 {
> #phy-cells = <4>;
> };
> lane3: lane@3 {
> #phy-cells = <4>;
> };
> };
>
> pinctrl_uart1_default: uart1-default {
This goes under a pinctrl node.
> mux {
> groups = "uart0_4_grp";
> function = "uart0";
> };
>
> conf {
> groups = "uart0_4_grp";
> slew-rate = ;
> io-standard = ;
> };
>
> conf-rx {
> pins = "MIO18";
> bias-high-impedance;
> };
>
> conf-tx {
> pins = "MIO19";
> bias-disable;
> schmitt-cmos = ;
> };
> };
> zynqmp-r5-remoteproc@0 {
Wrong unit-address and this doesn't belong here.
> compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
'remoteproc' is what the h/w block is called?
> reg = <0x0 0xFFE0 0x0 0x1>,
> <0x0 0xFFE2 0x0 0x1>,
> <0x0 0xff34 0x0 0x100>;
> reg-names = "tcm_a", "tcm_b", "ipi";
> dma-ranges;
> core_conf = "split0";
> memory-region = <_0_fw_reserved>,
> <_0_dma_reserved>;
> tcm-pnode-id = <0xf>, <0x10>;
> rpu-pnode-id = <0x7>;
> interrupt-parent = <>;
> interrupts = <0 29 4>;
> };
> };
> };
Re: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
On Fri, Nov 16, 2018 at 03:56:50PM -0800, Jolly Shah wrote:
> Base firmware node and clock child node binding are part of mainline kernel.
> This patchset adds documentation to describe rest of the firmware child node
> bindings.
> Complete firmware DT node example is shown below for ease of understanding:
Shouldn't there be a fpga mgr node too? Called pcap IIRC.
>
> firmware {
> zynqmp_firmware: zynqmp-firmware {
> compatible = "xlnx,zynqmp-firmware";
> method = "smc";
> #power-domain-cells = <1>;
> #reset-cells = <1>;
>
> zynqmp_clk: clock-controller {
> #clock-cells = <1>;
> compatible = "xlnx,zynqmp-clk";
> clocks = <_ref_clk>, <_clk>,
> <_alt_ref_clk>, <_ref_clk>, <_crx_ref_clk>;
> clock-names = "pss_ref_clk", "video_clk",
> "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
> };
>
> zynqmp_power: zynqmp-power {
> compatible = "xlnx,zynqmp-power";
> interrupts = <0 35 4>;
> };
>
> nvmem_firmware {
> compatible = "xlnx,zynqmp-nvmem-fw";
> #address-cells = <1>;
> #size-cells = <1>;
>
> /* Data cells */
> soc_revision: soc_revision {
> reg = <0x0 0x4>;
> };
> };
>
> afi0: afi0 {
> compatible = "xlnx,afi-fpga";
> config-afi = <0 2>, <1 1>, <2 1>;
> };
>
> qspi: spi@ff0f {
Why is this under firmware node?
> compatible = "xlnx,zynqmp-qspi-1.0";
> clock-names = "ref_clk", "pclk";
> clocks = <_clk _clk>;
> interrupts = <0 15 4>;
> interrupt-parent = <>;
> num-cs = <1>;
> reg = <0x0 0xff0f 0x1000>,<0x0 0xc000
> 0x800>;
> };
>
> serdes: zynqmp_phy@fd40 {
And this?
> compatible = "xlnx,zynqmp-psgtr";
> status = "okay";
> reg = <0x0 0xfd40 0x0 0x4>, <0x0 0xfd3d 0x0
> 0x1000>,
> <0x0 0xff5e 0x0 0x1000>;
> reg-names = "serdes", "siou", "lpd";
>
> lane0: lane@0 {
> #phy-cells = <4>;
> };
> lane1: lane@1 {
> #phy-cells = <4>;
> };
> lane2: lane@2 {
> #phy-cells = <4>;
> };
> lane3: lane@3 {
> #phy-cells = <4>;
> };
> };
>
> pinctrl_uart1_default: uart1-default {
This goes under a pinctrl node.
> mux {
> groups = "uart0_4_grp";
> function = "uart0";
> };
>
> conf {
> groups = "uart0_4_grp";
> slew-rate = ;
> io-standard = ;
> };
>
> conf-rx {
> pins = "MIO18";
> bias-high-impedance;
> };
>
> conf-tx {
> pins = "MIO19";
> bias-disable;
> schmitt-cmos = ;
> };
> };
> zynqmp-r5-remoteproc@0 {
Wrong unit-address and this doesn't belong here.
> compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
'remoteproc' is what the h/w block is called?
> reg = <0x0 0xFFE0 0x0 0x1>,
> <0x0 0xFFE2 0x0 0x1>,
> <0x0 0xff34 0x0 0x100>;
> reg-names = "tcm_a", "tcm_b", "ipi";
> dma-ranges;
> core_conf = "split0";
> memory-region = <_0_fw_reserved>,
> <_0_dma_reserved>;
> tcm-pnode-id = <0xf>, <0x10>;
> rpu-pnode-id = <0x7>;
> interrupt-parent = <>;
> interrupts = <0 29 4>;
> };
> };
> };
RE: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
Ping for comments
> -Original Message-
> From: Jolly Shah [mailto:jolly.s...@xilinx.com]
> Sent: Friday, November 16, 2018 3:57 PM
> To: robh...@kernel.org; mark.rutl...@arm.com
> Cc: Michal Simek ; Rajan Vaja ;
> Nava kishore Manne ; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicet...@vger.kernel.org; Jolly Shah
> Subject: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
>
> Base firmware node and clock child node binding are part of mainline kernel.
> This patchset adds documentation to describe rest of the firmware child node
> bindings.
> Complete firmware DT node example is shown below for ease of understanding:
>
> firmware {
> zynqmp_firmware: zynqmp-firmware {
> compatible = "xlnx,zynqmp-firmware";
> method = "smc";
> #power-domain-cells = <1>;
> #reset-cells = <1>;
>
> zynqmp_clk: clock-controller {
> #clock-cells = <1>;
> compatible = "xlnx,zynqmp-clk";
> clocks = <_ref_clk>, <_clk>,
> <_alt_ref_clk>, <_ref_clk>, <_crx_ref_clk>;
> clock-names = "pss_ref_clk", "video_clk",
> "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
> };
>
> zynqmp_power: zynqmp-power {
> compatible = "xlnx,zynqmp-power";
> interrupts = <0 35 4>;
> };
>
> nvmem_firmware {
> compatible = "xlnx,zynqmp-nvmem-fw";
> #address-cells = <1>;
> #size-cells = <1>;
>
> /* Data cells */
> soc_revision: soc_revision {
> reg = <0x0 0x4>;
> };
> };
>
> afi0: afi0 {
> compatible = "xlnx,afi-fpga";
> config-afi = <0 2>, <1 1>, <2 1>;
> };
>
> qspi: spi@ff0f {
> compatible = "xlnx,zynqmp-qspi-1.0";
> clock-names = "ref_clk", "pclk";
> clocks = <_clk _clk>;
> interrupts = <0 15 4>;
> interrupt-parent = <>;
> num-cs = <1>;
> reg = <0x0 0xff0f 0x1000>,<0x0 0xc000
> 0x800>;
> };
>
> serdes: zynqmp_phy@fd40 {
> compatible = "xlnx,zynqmp-psgtr";
> status = "okay";
> reg = <0x0 0xfd40 0x0 0x4>, <0x0 0xfd3d
> 0x0 0x1000>,
> <0x0 0xff5e 0x0 0x1000>;
> reg-names = "serdes", "siou", "lpd";
>
> lane0: lane@0 {
> #phy-cells = <4>;
> };
> lane1: lane@1 {
> #phy-cells = <4>;
> };
> lane2: lane@2 {
> #phy-cells = <4>;
> };
> lane3: lane@3 {
> #phy-cells = <4>;
> };
> };
>
> pinctrl_uart1_default: uart1-default {
> mux {
> groups = "uart0_4_grp";
> function = "uart0";
> };
>
> conf {
> groups = "uart0_4_grp";
> slew-rate = ;
> io-standard = ;
> };
>
> conf-rx {
> pins = "MIO18";
> bias-high-impedance;
> };
>
> conf-tx {
> pins = "MIO19";
> bias-disable;
> schmitt-cmos = ;
> };
> };
> zynqmp-r5-remoteproc@0 {
> compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
>
RE: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
Ping for comments
> -Original Message-
> From: Jolly Shah [mailto:jolly.s...@xilinx.com]
> Sent: Friday, November 16, 2018 3:57 PM
> To: robh...@kernel.org; mark.rutl...@arm.com
> Cc: Michal Simek ; Rajan Vaja ;
> Nava kishore Manne ; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicet...@vger.kernel.org; Jolly Shah
> Subject: [PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
>
> Base firmware node and clock child node binding are part of mainline kernel.
> This patchset adds documentation to describe rest of the firmware child node
> bindings.
> Complete firmware DT node example is shown below for ease of understanding:
>
> firmware {
> zynqmp_firmware: zynqmp-firmware {
> compatible = "xlnx,zynqmp-firmware";
> method = "smc";
> #power-domain-cells = <1>;
> #reset-cells = <1>;
>
> zynqmp_clk: clock-controller {
> #clock-cells = <1>;
> compatible = "xlnx,zynqmp-clk";
> clocks = <_ref_clk>, <_clk>,
> <_alt_ref_clk>, <_ref_clk>, <_crx_ref_clk>;
> clock-names = "pss_ref_clk", "video_clk",
> "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
> };
>
> zynqmp_power: zynqmp-power {
> compatible = "xlnx,zynqmp-power";
> interrupts = <0 35 4>;
> };
>
> nvmem_firmware {
> compatible = "xlnx,zynqmp-nvmem-fw";
> #address-cells = <1>;
> #size-cells = <1>;
>
> /* Data cells */
> soc_revision: soc_revision {
> reg = <0x0 0x4>;
> };
> };
>
> afi0: afi0 {
> compatible = "xlnx,afi-fpga";
> config-afi = <0 2>, <1 1>, <2 1>;
> };
>
> qspi: spi@ff0f {
> compatible = "xlnx,zynqmp-qspi-1.0";
> clock-names = "ref_clk", "pclk";
> clocks = <_clk _clk>;
> interrupts = <0 15 4>;
> interrupt-parent = <>;
> num-cs = <1>;
> reg = <0x0 0xff0f 0x1000>,<0x0 0xc000
> 0x800>;
> };
>
> serdes: zynqmp_phy@fd40 {
> compatible = "xlnx,zynqmp-psgtr";
> status = "okay";
> reg = <0x0 0xfd40 0x0 0x4>, <0x0 0xfd3d
> 0x0 0x1000>,
> <0x0 0xff5e 0x0 0x1000>;
> reg-names = "serdes", "siou", "lpd";
>
> lane0: lane@0 {
> #phy-cells = <4>;
> };
> lane1: lane@1 {
> #phy-cells = <4>;
> };
> lane2: lane@2 {
> #phy-cells = <4>;
> };
> lane3: lane@3 {
> #phy-cells = <4>;
> };
> };
>
> pinctrl_uart1_default: uart1-default {
> mux {
> groups = "uart0_4_grp";
> function = "uart0";
> };
>
> conf {
> groups = "uart0_4_grp";
> slew-rate = ;
> io-standard = ;
> };
>
> conf-rx {
> pins = "MIO18";
> bias-high-impedance;
> };
>
> conf-tx {
> pins = "MIO19";
> bias-disable;
> schmitt-cmos = ;
> };
> };
> zynqmp-r5-remoteproc@0 {
> compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
>
[PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
Base firmware node and clock child node binding are part of mainline kernel.
This patchset adds documentation to describe rest of the firmware child node
bindings.
Complete firmware DT node example is shown below for ease of understanding:
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
#power-domain-cells = <1>;
#reset-cells = <1>;
zynqmp_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <_ref_clk>, <_clk>,
<_alt_ref_clk>, <_ref_clk>, <_crx_ref_clk>;
clock-names = "pss_ref_clk", "video_clk",
"pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
};
zynqmp_power: zynqmp-power {
compatible = "xlnx,zynqmp-power";
interrupts = <0 35 4>;
};
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;
/* Data cells */
soc_revision: soc_revision {
reg = <0x0 0x4>;
};
};
afi0: afi0 {
compatible = "xlnx,afi-fpga";
config-afi = <0 2>, <1 1>, <2 1>;
};
qspi: spi@ff0f {
compatible = "xlnx,zynqmp-qspi-1.0";
clock-names = "ref_clk", "pclk";
clocks = <_clk _clk>;
interrupts = <0 15 4>;
interrupt-parent = <>;
num-cs = <1>;
reg = <0x0 0xff0f 0x1000>,<0x0 0xc000
0x800>;
};
serdes: zynqmp_phy@fd40 {
compatible = "xlnx,zynqmp-psgtr";
status = "okay";
reg = <0x0 0xfd40 0x0 0x4>, <0x0 0xfd3d 0x0
0x1000>,
<0x0 0xff5e 0x0 0x1000>;
reg-names = "serdes", "siou", "lpd";
lane0: lane@0 {
#phy-cells = <4>;
};
lane1: lane@1 {
#phy-cells = <4>;
};
lane2: lane@2 {
#phy-cells = <4>;
};
lane3: lane@3 {
#phy-cells = <4>;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = ;
io-standard = ;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
schmitt-cmos = ;
};
};
zynqmp-r5-remoteproc@0 {
compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
reg = <0x0 0xFFE0 0x0 0x1>,
<0x0 0xFFE2 0x0 0x1>,
<0x0 0xff34 0x0 0x100>;
reg-names = "tcm_a", "tcm_b", "ipi";
dma-ranges;
core_conf = "split0";
memory-region = <_0_fw_reserved>,
<_0_dma_reserved>;
tcm-pnode-id = <0xf>, <0x10>;
rpu-pnode-id = <0x7>;
interrupt-parent = <>;
interrupts = <0 29 4>;
};
};
};
Jolly Shah (2):
dt-bindings: phy: Add dt bindings for ZynqMP PHY
dt-bindings: fpga: Add binding doc for the afi config driver
Nava kishore Manne (2):
dt-bindings: reset: Add bindings for ZynqMP reset driver
dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
Rajan Vaja (4):
dt-bindings: power: Add ZynqMP power domain bindings
dt-bindings: soc: Add ZynqMP PM bindings
dt-bindings: pinctrl: Add ZynqMP pin controller bindings
dt-bindings: spi: zynqmp: Move SPI node under zynqmp firmware
Wendy Liang (1):
dt-bindings: remoteproc: Add Xilinx
[PATCH 0/9] dt-bindings: Firmware node binding for ZynqMP core
Base firmware node and clock child node binding are part of mainline kernel.
This patchset adds documentation to describe rest of the firmware child node
bindings.
Complete firmware DT node example is shown below for ease of understanding:
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
#power-domain-cells = <1>;
#reset-cells = <1>;
zynqmp_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <_ref_clk>, <_clk>,
<_alt_ref_clk>, <_ref_clk>, <_crx_ref_clk>;
clock-names = "pss_ref_clk", "video_clk",
"pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
};
zynqmp_power: zynqmp-power {
compatible = "xlnx,zynqmp-power";
interrupts = <0 35 4>;
};
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;
/* Data cells */
soc_revision: soc_revision {
reg = <0x0 0x4>;
};
};
afi0: afi0 {
compatible = "xlnx,afi-fpga";
config-afi = <0 2>, <1 1>, <2 1>;
};
qspi: spi@ff0f {
compatible = "xlnx,zynqmp-qspi-1.0";
clock-names = "ref_clk", "pclk";
clocks = <_clk _clk>;
interrupts = <0 15 4>;
interrupt-parent = <>;
num-cs = <1>;
reg = <0x0 0xff0f 0x1000>,<0x0 0xc000
0x800>;
};
serdes: zynqmp_phy@fd40 {
compatible = "xlnx,zynqmp-psgtr";
status = "okay";
reg = <0x0 0xfd40 0x0 0x4>, <0x0 0xfd3d 0x0
0x1000>,
<0x0 0xff5e 0x0 0x1000>;
reg-names = "serdes", "siou", "lpd";
lane0: lane@0 {
#phy-cells = <4>;
};
lane1: lane@1 {
#phy-cells = <4>;
};
lane2: lane@2 {
#phy-cells = <4>;
};
lane3: lane@3 {
#phy-cells = <4>;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = ;
io-standard = ;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
schmitt-cmos = ;
};
};
zynqmp-r5-remoteproc@0 {
compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
reg = <0x0 0xFFE0 0x0 0x1>,
<0x0 0xFFE2 0x0 0x1>,
<0x0 0xff34 0x0 0x100>;
reg-names = "tcm_a", "tcm_b", "ipi";
dma-ranges;
core_conf = "split0";
memory-region = <_0_fw_reserved>,
<_0_dma_reserved>;
tcm-pnode-id = <0xf>, <0x10>;
rpu-pnode-id = <0x7>;
interrupt-parent = <>;
interrupts = <0 29 4>;
};
};
};
Jolly Shah (2):
dt-bindings: phy: Add dt bindings for ZynqMP PHY
dt-bindings: fpga: Add binding doc for the afi config driver
Nava kishore Manne (2):
dt-bindings: reset: Add bindings for ZynqMP reset driver
dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
Rajan Vaja (4):
dt-bindings: power: Add ZynqMP power domain bindings
dt-bindings: soc: Add ZynqMP PM bindings
dt-bindings: pinctrl: Add ZynqMP pin controller bindings
dt-bindings: spi: zynqmp: Move SPI node under zynqmp firmware
Wendy Liang (1):
dt-bindings: remoteproc: Add Xilinx
