From: Andi Kleen
Add support for the v2 PEBS format. It has a superset of the v1 PEBS
fields, but has a longer record so we need to adjust the code paths.
The main advantage is the new "EventingRip" support which directly
gives the instruction, not off-by-one instruction. So with precise == 2
From: Andi Kleen a...@linux.intel.com
Add support for the v2 PEBS format. It has a superset of the v1 PEBS
fields, but has a longer record so we need to adjust the code paths.
The main advantage is the new EventingRip support which directly
gives the instruction, not off-by-one instruction. So
On Fri, Sep 28, 2012 at 10:43:04AM +0200, Peter Zijlstra wrote:
> On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
> > + if (event->attr.precise_ip > 1 &&
> > x86_pmu.intel_cap.pebs_format < 2) {
>
> Shouldn't that be: && x86_pmu.intel_cap.pebs_trap, like most other sites
>
On Fri, Sep 28, 2012 at 11:28 AM, Peter Zijlstra wrote:
> On Fri, 2012-09-28 at 10:54 +0200, Stephane Eranian wrote:
>> On Fri, Sep 28, 2012 at 10:43 AM, Peter Zijlstra
>> wrote:
>> > On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
>> >> + if (event->attr.precise_ip > 1 &&
On Fri, 2012-09-28 at 10:54 +0200, Stephane Eranian wrote:
> On Fri, Sep 28, 2012 at 10:43 AM, Peter Zijlstra
> wrote:
> > On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
> >> + if (event->attr.precise_ip > 1 &&
> >> x86_pmu.intel_cap.pebs_format < 2) {
> >
> > Shouldn't that
On Fri, Sep 28, 2012 at 10:43 AM, Peter Zijlstra wrote:
> On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
>> + if (event->attr.precise_ip > 1 &&
>> x86_pmu.intel_cap.pebs_format < 2) {
>
> Shouldn't that be: && x86_pmu.intel_cap.pebs_trap, like most other sites
> instead? Or
On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
> + if (event->attr.precise_ip > 1 &&
> x86_pmu.intel_cap.pebs_format < 2) {
Shouldn't that be: && x86_pmu.intel_cap.pebs_trap, like most other sites
instead? Or didn't they flip the trap capability on Haswell?
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On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
+ if (event-attr.precise_ip 1
x86_pmu.intel_cap.pebs_format 2) {
Shouldn't that be: x86_pmu.intel_cap.pebs_trap, like most other sites
instead? Or didn't they flip the trap capability on Haswell?
--
To unsubscribe from this
On Fri, Sep 28, 2012 at 10:43 AM, Peter Zijlstra a.p.zijls...@chello.nl wrote:
On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
+ if (event-attr.precise_ip 1
x86_pmu.intel_cap.pebs_format 2) {
Shouldn't that be: x86_pmu.intel_cap.pebs_trap, like most other sites
On Fri, 2012-09-28 at 10:54 +0200, Stephane Eranian wrote:
On Fri, Sep 28, 2012 at 10:43 AM, Peter Zijlstra a.p.zijls...@chello.nl
wrote:
On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
+ if (event-attr.precise_ip 1
x86_pmu.intel_cap.pebs_format 2) {
Shouldn't
On Fri, Sep 28, 2012 at 11:28 AM, Peter Zijlstra a.p.zijls...@chello.nl wrote:
On Fri, 2012-09-28 at 10:54 +0200, Stephane Eranian wrote:
On Fri, Sep 28, 2012 at 10:43 AM, Peter Zijlstra a.p.zijls...@chello.nl
wrote:
On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
+ if
On Fri, Sep 28, 2012 at 10:43:04AM +0200, Peter Zijlstra wrote:
On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
+ if (event-attr.precise_ip 1
x86_pmu.intel_cap.pebs_format 2) {
Shouldn't that be: x86_pmu.intel_cap.pebs_trap, like most other sites
instead? Or didn't
From: Andi Kleen
Add support for the v2 PEBS format. It has a superset of the v1 PEBS
fields, but has a longer record so we need to adjust the code paths.
The main advantage is the new "EventingRip" support which directly
gives the instruction, not off-by-one instruction. So with precise == 2
From: Andi Kleen a...@linux.intel.com
Add support for the v2 PEBS format. It has a superset of the v1 PEBS
fields, but has a longer record so we need to adjust the code paths.
The main advantage is the new EventingRip support which directly
gives the instruction, not off-by-one instruction. So
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