[PATCH 02/15] ARM: dts: ipq4019: Add a few peripheral nodes

2018-01-28 Thread Sricharan R 
Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.

Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 
 1 file changed, 134 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 10d112a..e38fffa 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -25,7 +25,9 @@
 
aliases {
spi0 = _0;
+   spi1 = _1;
i2c0 = _0;
+   i2c1 = _1;
};
 
cpus {
@@ -104,6 +106,12 @@
};
};
 
+   firmware {
+   scm {
+   compatible = "qcom,scm-ipq4019";
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
@@ -172,6 +180,22 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <_dma 5>, <_dma 4>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   spi_1: spi@78b6000 { /* BLSP1 QUP2 */
+   compatible = "qcom,spi-qup-v2.2.1";
+   reg = <0x78b6000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <_dma 7>, <_dma 6>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
@@ -184,9 +208,24 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <_dma 9>, <_dma 8>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
+   i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
+   compatible = "qcom,i2c-qup-v2.2.1";
+   reg = <0x78b8000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>,
+< GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <_dma 11>, <_dma 10>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
 
cryptobam: dma@8e04000 {
compatible = "qcom,bam-v1.7.0";
@@ -293,6 +332,101 @@
reg = <0x4ab000 0x4>;
};
 
+   pcie0: pci@4000 {
+   compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
+   reg =  <0x4000 0xf1d
+   0x4f20 0xa8
+   0x8 0x2000
+   0x4010 0x1000>;
+   reg-names = "dbi", "elbi", "parf", "config";
+   device_type = "pci";
+   linux,pci-domain = <0>;
+   bus-range = <0x00 0xff>;
+   num-lanes = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+
+   ranges = <0x8100 0 0x4020 0x4020 0 
0x0010
+ 0x8200 0 0x4800 0x4800 0 
0x1000>;
+
+   interrupts = ;
+   interrupt-names = "msi";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0x7>;
+   interrupt-map = <0 0 0 1  0 142 
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+   <0 0 0 2  0 143 
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+   <0 0 0 3  0 144 
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+   <0 0 0 4  0 145 
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+   clocks = < GCC_PCIE_AHB_CLK>,
+< GCC_PCIE_AXI_M_CLK>,
+< GCC_PCIE_AXI_S_CLK>;
+   clock-names = "aux",
+ "master_bus",
+ "slave_bus";
+
+   resets = < PCIE_AXI_M_ARES>,
+< PCIE_AXI_S_ARES>,
+< PCIE_PIPE_ARES>,
+<

[PATCH 02/15] ARM: dts: ipq4019: Add a few peripheral nodes

2018-01-28 Thread Sricharan R 
Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.

Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 
 1 file changed, 134 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 10d112a..e38fffa 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -25,7 +25,9 @@
 
aliases {
spi0 = _0;
+   spi1 = _1;
i2c0 = _0;
+   i2c1 = _1;
};
 
cpus {
@@ -104,6 +106,12 @@
};
};
 
+   firmware {
+   scm {
+   compatible = "qcom,scm-ipq4019";
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
@@ -172,6 +180,22 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <_dma 5>, <_dma 4>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   spi_1: spi@78b6000 { /* BLSP1 QUP2 */
+   compatible = "qcom,spi-qup-v2.2.1";
+   reg = <0x78b6000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <_dma 7>, <_dma 6>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
@@ -184,9 +208,24 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <_dma 9>, <_dma 8>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
+   i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
+   compatible = "qcom,i2c-qup-v2.2.1";
+   reg = <0x78b8000 0x600>;
+   interrupts = ;
+   clocks = < GCC_BLSP1_AHB_CLK>,
+< GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <_dma 11>, <_dma 10>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
 
cryptobam: dma@8e04000 {
compatible = "qcom,bam-v1.7.0";
@@ -293,6 +332,101 @@
reg = <0x4ab000 0x4>;
};
 
+   pcie0: pci@4000 {
+   compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
+   reg =  <0x4000 0xf1d
+   0x4f20 0xa8
+   0x8 0x2000
+   0x4010 0x1000>;
+   reg-names = "dbi", "elbi", "parf", "config";
+   device_type = "pci";
+   linux,pci-domain = <0>;
+   bus-range = <0x00 0xff>;
+   num-lanes = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+
+   ranges = <0x8100 0 0x4020 0x4020 0 
0x0010
+ 0x8200 0 0x4800 0x4800 0 
0x1000>;
+
+   interrupts = ;
+   interrupt-names = "msi";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0x7>;
+   interrupt-map = <0 0 0 1  0 142 
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+   <0 0 0 2  0 143 
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+   <0 0 0 3  0 144 
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+   <0 0 0 4  0 145 
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+   clocks = < GCC_PCIE_AHB_CLK>,
+< GCC_PCIE_AXI_M_CLK>,
+< GCC_PCIE_AXI_S_CLK>;
+   clock-names = "aux",
+ "master_bus",
+ "slave_bus";
+
+   resets = < PCIE_AXI_M_ARES>,
+< PCIE_AXI_S_ARES>,
+< PCIE_PIPE_ARES>,
+< PCIE_AXI_M_VMIDMT_ARES>,
+