> Do things like the 0xd0 event really need all the UEVENT things spelled
> out?
There were some missing unit masks, so I spelled it out.
> And 0x22d0 (LOCK_STORES) still appears missing going by the pattern
> in there.
Will double check.
> Also, it looks like the 0xc5 things want to be
On Thu, 2012-10-18 at 16:19 -0700, Andi Kleen wrote:
> +struct event_constraint intel_hsw_pebs_event_constraints[] = {
> + INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
> + INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
> +
On Thu, 2012-10-18 at 16:19 -0700, Andi Kleen wrote:
+struct event_constraint intel_hsw_pebs_event_constraints[] = {
+ INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
+ INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
+
Do things like the 0xd0 event really need all the UEVENT things spelled
out?
There were some missing unit masks, so I spelled it out.
And 0x22d0 (LOCK_STORES) still appears missing going by the pattern
in there.
Will double check.
Also, it looks like the 0xc5 things want to be UEVENT,
From: Andi Kleen
Add basic PEBS support for Haswell.
The constraints are similar to SandyBridge with a few new events.
v2: Readd missing pebs_aliases
Signed-off-by: Andi Kleen
---
arch/x86/kernel/cpu/perf_event.h |2 ++
arch/x86/kernel/cpu/perf_event_intel.c|3 ++-
From: Andi Kleen a...@linux.intel.com
Add basic PEBS support for Haswell.
The constraints are similar to SandyBridge with a few new events.
v2: Readd missing pebs_aliases
Signed-off-by: Andi Kleen a...@linux.intel.com
---
arch/x86/kernel/cpu/perf_event.h |2 ++
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