On 8/11/2012 3:17 AM, Marc Zyngier wrote:
On Fri, 10 Aug 2012 14:57:34 -0700, Rohit Vaswani
wrote:
Level triggered interrupt is deasserted when a new TVAL is written
only when the interrupt is unmasked. Make sure that the interrupt
is unmasked in CTL register before TVAL is written.
If this
On 8/11/2012 3:17 AM, Marc Zyngier wrote:
On Fri, 10 Aug 2012 14:57:34 -0700, Rohit Vaswani
rvasw...@codeaurora.org
wrote:
Level triggered interrupt is deasserted when a new TVAL is written
only when the interrupt is unmasked. Make sure that the interrupt
is unmasked in CTL register before TVAL
On Fri, 10 Aug 2012 14:57:34 -0700, Rohit Vaswani
wrote:
> Level triggered interrupt is deasserted when a new TVAL is written
> only when the interrupt is unmasked. Make sure that the interrupt
> is unmasked in CTL register before TVAL is written.
> If this order is not followed, there are
On Fri, 10 Aug 2012 14:57:34 -0700, Rohit Vaswani
rvasw...@codeaurora.org
wrote:
Level triggered interrupt is deasserted when a new TVAL is written
only when the interrupt is unmasked. Make sure that the interrupt
is unmasked in CTL register before TVAL is written.
If this order is not
Level triggered interrupt is deasserted when a new TVAL is written
only when the interrupt is unmasked. Make sure that the interrupt
is unmasked in CTL register before TVAL is written.
If this order is not followed, there are chances that on some
hardware you would not receive any timer
Level triggered interrupt is deasserted when a new TVAL is written
only when the interrupt is unmasked. Make sure that the interrupt
is unmasked in CTL register before TVAL is written.
If this order is not followed, there are chances that on some
hardware you would not receive any timer
6 matches
Mail list logo