Re: [PATCH 1/2] clk: tegra30: Add hda clock default rates to clock driver

[Jon Hunter]

On 25/12/2020 01:20, Peter Geis wrote:
> Current implementation defaults the hda clocks to clk_m.
> This causes hda to run too slow to operate correctly.
> Fix this by defaulting to pll_p and setting the frequency to the correct rate.
> 
> This matches upstream t124 and downstream t30.
> 
> Signed-off-by: Peter Geis 
> Tested-by: Ion Agorria 
> ---
>  drivers/clk/tegra/clk-tegra30.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
> index 37244a7e68c2..9cf249c344d9 100644
> --- a/drivers/clk/tegra/clk-tegra30.c
> +++ b/drivers/clk/tegra/clk-tegra30.c
> @@ -1256,6 +1256,8 @@ static struct tegra_clk_init_table init_table[] 
> __initdata = {
>   { TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 2400, 0 },
>   { TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 2400, 0 },
>   { TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 2400, 0 },
> + { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 10200, 0 },
> + { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 4800, 0 },
>   /* must be the last entry */
>   { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
>  };


This looks good to me. So ...

Acked-by: Jon Hunter 

Cheers
Jon

-- 
nvpublic

[PATCH 1/2] clk: tegra30: Add hda clock default rates to clock driver

[Peter Geis]

Current implementation defaults the hda clocks to clk_m.
This causes hda to run too slow to operate correctly.
Fix this by defaulting to pll_p and setting the frequency to the correct rate.

This matches upstream t124 and downstream t30.

Signed-off-by: Peter Geis 
Tested-by: Ion Agorria 
---
 drivers/clk/tegra/clk-tegra30.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 37244a7e68c2..9cf249c344d9 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1256,6 +1256,8 @@ static struct tegra_clk_init_table init_table[] 
__initdata = {
{ TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 2400, 0 },
{ TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 2400, 0 },
{ TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 2400, 0 },
+   { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 10200, 0 },
+   { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 4800, 0 },
/* must be the last entry */
{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
 };
-- 
2.25.1