On Tue, Jul 14, 2020 at 07:50:43AM +0100, Lee Jones wrote:
> On Tue, 14 Jul 2020, Xu Yilun wrote:
>
> > On Mon, Jul 13, 2020 at 10:17:08AM +0100, Lee Jones wrote:
> > > On Mon, 13 Jul 2020, Xu Yilun wrote:
> > >
> > > > This patch implements the basic functions of the BMC chip for some Intel
> >
On Tue, 14 Jul 2020, Xu Yilun wrote:
> On Mon, Jul 13, 2020 at 10:17:08AM +0100, Lee Jones wrote:
> > On Mon, 13 Jul 2020, Xu Yilun wrote:
> >
> > > This patch implements the basic functions of the BMC chip for some Intel
> > > FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the
On Mon, Jul 13, 2020 at 10:17:08AM +0100, Lee Jones wrote:
> On Mon, 13 Jul 2020, Xu Yilun wrote:
>
> > This patch implements the basic functions of the BMC chip for some Intel
> > FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the
> > intel max10 CPLD.
> >
> > This BMC chip is
On Mon, 13 Jul 2020, Xu Yilun wrote:
> This patch implements the basic functions of the BMC chip for some Intel
> FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the
> intel max10 CPLD.
>
> This BMC chip is connected to FPGA by a SPI bus. To provide reliable
> register access
This patch implements the basic functions of the BMC chip for some Intel
FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the
intel max10 CPLD.
This BMC chip is connected to FPGA by a SPI bus. To provide reliable
register access from FPGA, an Avalon Memory-Mapped (Avmm)
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