Re: [PATCH 1/2] mfd: intel-m10-bmc: add Max10 BMC chip support for Intel FPGA PAC

2020-07-14 Thread Xu Yilun
On Tue, Jul 14, 2020 at 07:50:43AM +0100, Lee Jones wrote: > On Tue, 14 Jul 2020, Xu Yilun wrote: > > > On Mon, Jul 13, 2020 at 10:17:08AM +0100, Lee Jones wrote: > > > On Mon, 13 Jul 2020, Xu Yilun wrote: > > > > > > > This patch implements the basic functions of the BMC chip for some Intel > >

Re: [PATCH 1/2] mfd: intel-m10-bmc: add Max10 BMC chip support for Intel FPGA PAC

2020-07-14 Thread Lee Jones
On Tue, 14 Jul 2020, Xu Yilun wrote: > On Mon, Jul 13, 2020 at 10:17:08AM +0100, Lee Jones wrote: > > On Mon, 13 Jul 2020, Xu Yilun wrote: > > > > > This patch implements the basic functions of the BMC chip for some Intel > > > FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the

Re: [PATCH 1/2] mfd: intel-m10-bmc: add Max10 BMC chip support for Intel FPGA PAC

2020-07-14 Thread Xu Yilun
On Mon, Jul 13, 2020 at 10:17:08AM +0100, Lee Jones wrote: > On Mon, 13 Jul 2020, Xu Yilun wrote: > > > This patch implements the basic functions of the BMC chip for some Intel > > FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the > > intel max10 CPLD. > > > > This BMC chip is

Re: [PATCH 1/2] mfd: intel-m10-bmc: add Max10 BMC chip support for Intel FPGA PAC

2020-07-13 Thread Lee Jones
On Mon, 13 Jul 2020, Xu Yilun wrote: > This patch implements the basic functions of the BMC chip for some Intel > FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the > intel max10 CPLD. > > This BMC chip is connected to FPGA by a SPI bus. To provide reliable > register access

[PATCH 1/2] mfd: intel-m10-bmc: add Max10 BMC chip support for Intel FPGA PAC

2020-07-12 Thread Xu Yilun
This patch implements the basic functions of the BMC chip for some Intel FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the intel max10 CPLD. This BMC chip is connected to FPGA by a SPI bus. To provide reliable register access from FPGA, an Avalon Memory-Mapped (Avmm)