On Thu 21 Jun 08:14 PDT 2018, Stephen Boyd wrote:
> Quoting Bjorn Andersson (2018-06-19 23:45:09)
> > On Mon 18 Jun 13:52 PDT 2018, Stephen Boyd wrote:
> > > @@ -647,6 +660,10 @@ static void msm_gpio_irq_unmask(struct irq_data *d)
> > > raw_spin_lock_irqsave(>lock, flags);
> > >
> > >
On Thu 21 Jun 08:14 PDT 2018, Stephen Boyd wrote:
> Quoting Bjorn Andersson (2018-06-19 23:45:09)
> > On Mon 18 Jun 13:52 PDT 2018, Stephen Boyd wrote:
> > > @@ -647,6 +660,10 @@ static void msm_gpio_irq_unmask(struct irq_data *d)
> > > raw_spin_lock_irqsave(>lock, flags);
> > >
> > >
Quoting Bjorn Andersson (2018-06-19 23:45:09)
> On Mon 18 Jun 13:52 PDT 2018, Stephen Boyd wrote:
> > @@ -647,6 +660,10 @@ static void msm_gpio_irq_unmask(struct irq_data *d)
> > raw_spin_lock_irqsave(>lock, flags);
> >
> > val = readl(pctrl->regs + g->intr_cfg_reg);
> > + if
Quoting Bjorn Andersson (2018-06-19 23:45:09)
> On Mon 18 Jun 13:52 PDT 2018, Stephen Boyd wrote:
> > @@ -647,6 +660,10 @@ static void msm_gpio_irq_unmask(struct irq_data *d)
> > raw_spin_lock_irqsave(>lock, flags);
> >
> > val = readl(pctrl->regs + g->intr_cfg_reg);
> > + if
Hi,
On Tue, Jun 19, 2018 at 11:45 PM, Bjorn Andersson
wrote:
> On Mon 18 Jun 13:52 PDT 2018, Stephen Boyd wrote:
>
>> The interrupt controller hardware in this pin controller has two status
>> enable bits. The first "normal" status enable bit enables or disables
>> the summary interrupt line
Hi,
On Tue, Jun 19, 2018 at 11:45 PM, Bjorn Andersson
wrote:
> On Mon 18 Jun 13:52 PDT 2018, Stephen Boyd wrote:
>
>> The interrupt controller hardware in this pin controller has two status
>> enable bits. The first "normal" status enable bit enables or disables
>> the summary interrupt line
On Mon 18 Jun 13:52 PDT 2018, Stephen Boyd wrote:
> The interrupt controller hardware in this pin controller has two status
> enable bits. The first "normal" status enable bit enables or disables
> the summary interrupt line being raised when a gpio interrupt triggers
> and the "raw" status
On Mon 18 Jun 13:52 PDT 2018, Stephen Boyd wrote:
> The interrupt controller hardware in this pin controller has two status
> enable bits. The first "normal" status enable bit enables or disables
> the summary interrupt line being raised when a gpio interrupt triggers
> and the "raw" status
Quoting Doug Anderson (2018-06-18 16:38:27)
> Hi,
>
> On Mon, Jun 18, 2018 at 4:28 PM, Stephen Boyd wrote:
> > Quoting Doug Anderson (2018-06-18 15:43:06)
> >>
> >> On Mon, Jun 18, 2018 at 1:52 PM, Stephen Boyd wrote:
> >>
> >> > +*/
> >> > + if (irqd_get_trigger_type(d) &
Quoting Doug Anderson (2018-06-18 16:38:27)
> Hi,
>
> On Mon, Jun 18, 2018 at 4:28 PM, Stephen Boyd wrote:
> > Quoting Doug Anderson (2018-06-18 15:43:06)
> >>
> >> On Mon, Jun 18, 2018 at 1:52 PM, Stephen Boyd wrote:
> >>
> >> > +*/
> >> > + if (irqd_get_trigger_type(d) &
Hi,
On Mon, Jun 18, 2018 at 4:28 PM, Stephen Boyd wrote:
> Quoting Doug Anderson (2018-06-18 15:43:06)
>>
>> On Mon, Jun 18, 2018 at 1:52 PM, Stephen Boyd wrote:
>>
>> > +*/
>> > + if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK) {
>> > + val &=
Hi,
On Mon, Jun 18, 2018 at 4:28 PM, Stephen Boyd wrote:
> Quoting Doug Anderson (2018-06-18 15:43:06)
>>
>> On Mon, Jun 18, 2018 at 1:52 PM, Stephen Boyd wrote:
>>
>> > +*/
>> > + if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK) {
>> > + val &=
Quoting Doug Anderson (2018-06-18 15:43:06)
>
> On Mon, Jun 18, 2018 at 1:52 PM, Stephen Boyd wrote:
>
> > +*/
> > + if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK) {
> > + val &= ~BIT(g->intr_raw_status_bit);
> > + writel(val, pctrl->regs +
Quoting Doug Anderson (2018-06-18 15:43:06)
>
> On Mon, Jun 18, 2018 at 1:52 PM, Stephen Boyd wrote:
>
> > +*/
> > + if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK) {
> > + val &= ~BIT(g->intr_raw_status_bit);
> > + writel(val, pctrl->regs +
Hi,
On Mon, Jun 18, 2018 at 1:52 PM, Stephen Boyd wrote:
> The interrupt controller hardware in this pin controller has two status
> enable bits. The first "normal" status enable bit enables or disables
> the summary interrupt line being raised when a gpio interrupt triggers
> and the "raw"
Hi,
On Mon, Jun 18, 2018 at 1:52 PM, Stephen Boyd wrote:
> The interrupt controller hardware in this pin controller has two status
> enable bits. The first "normal" status enable bit enables or disables
> the summary interrupt line being raised when a gpio interrupt triggers
> and the "raw"
The interrupt controller hardware in this pin controller has two status
enable bits. The first "normal" status enable bit enables or disables
the summary interrupt line being raised when a gpio interrupt triggers
and the "raw" status enable bit allows or prevents the hardware from
latching an
The interrupt controller hardware in this pin controller has two status
enable bits. The first "normal" status enable bit enables or disables
the summary interrupt line being raised when a gpio interrupt triggers
and the "raw" status enable bit allows or prevents the hardware from
latching an
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