[PATCH 1/4] fsl: add EPU FSM configuration for deep sleep
T104x, T1024 and LS1021 of Freescale have a Finite State Machine (FSM)
to control the hardware precedure in deep sleep. Software will start
the FSM to enter deep sleep after finishing prepare work.
Then, when receiving a wakeup event, the FSM will restore the SoC to
work.
This driver configures and clears the FSM registers for deep sleep. Note
that the sequence of clearing the FSM registers does matter, should follow
the sequence mentioned in the reference manual.
Signed-off-by: Chenhui Zhao
---
drivers/platform/Kconfig | 2 +
drivers/platform/Makefile| 1 +
drivers/platform/fsl/Kconfig | 11 ++
drivers/platform/fsl/Makefile| 5 +
drivers/platform/fsl/sleep_fsm.c | 263 +++
drivers/platform/fsl/sleep_fsm.h | 104
6 files changed, 386 insertions(+)
create mode 100644 drivers/platform/fsl/Kconfig
create mode 100644 drivers/platform/fsl/Makefile
create mode 100644 drivers/platform/fsl/sleep_fsm.c
create mode 100644 drivers/platform/fsl/sleep_fsm.h
diff --git a/drivers/platform/Kconfig b/drivers/platform/Kconfig
index 09fde58..85e3c95 100644
--- a/drivers/platform/Kconfig
+++ b/drivers/platform/Kconfig
@@ -6,3 +6,5 @@ source "drivers/platform/goldfish/Kconfig"
endif
source "drivers/platform/chrome/Kconfig"
+
+source "drivers/platform/fsl/Kconfig"
diff --git a/drivers/platform/Makefile b/drivers/platform/Makefile
index 3656b7b..37c6f72 100644
--- a/drivers/platform/Makefile
+++ b/drivers/platform/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_X86) += x86/
obj-$(CONFIG_OLPC) += olpc/
obj-$(CONFIG_GOLDFISH) += goldfish/
obj-$(CONFIG_CHROME_PLATFORMS) += chrome/
+obj-$(CONFIG_FSL_SOC) += fsl/
diff --git a/drivers/platform/fsl/Kconfig b/drivers/platform/fsl/Kconfig
new file mode 100644
index 000..a1ea46e
--- /dev/null
+++ b/drivers/platform/fsl/Kconfig
@@ -0,0 +1,11 @@
+#
+# Freescale Specific Power Management Drivers
+#
+
+config FSL_SLEEP_FSM
+ bool
+ help
+ This driver configures a hardware FSM (Finite State Machine) used in
deep sleep.
+ The FSM finishes clean-ups at the last stage of entering deep sleep,
and also
+ wakes up system when a wake up event happens. So far, T104x, T1024
and LS1021
+ need this.
diff --git a/drivers/platform/fsl/Makefile b/drivers/platform/fsl/Makefile
new file mode 100644
index 000..d99ca0e
--- /dev/null
+++ b/drivers/platform/fsl/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for linux/drivers/platform/fsl
+# Freescale Specific Power Management Drivers
+#
+obj-$(CONFIG_FSL_SLEEP_FSM)+= sleep_fsm.o
diff --git a/drivers/platform/fsl/sleep_fsm.c b/drivers/platform/fsl/sleep_fsm.c
new file mode 100644
index 000..0a0480a
--- /dev/null
+++ b/drivers/platform/fsl/sleep_fsm.c
@@ -0,0 +1,263 @@
+/*
+ * Freescale deep sleep FSM (finite-state machine) configuration
+ *
+ * Copyright 2014-2015 Freescale Semiconductor Inc.
+ *
+ * Author: Hongbo Zhang
+ * Chenhui Zhao
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include
+#include
+#include
+
+#include "sleep_fsm.h"
+/*
+ * These values are from chip's reference manual. For example,
+ * the values for T1040 can be found in "8.4.3.8 Programming
+ * supporting deep sleep mode" of Chapter 8 "Run Control and
+ * Power Management (RCPM)".
+ * The default value can be applied to T104x, T1024 and LS1021.
+ */
+struct fsm_reg_vals epu_default_val[] = {
+ /* EPGCR (Event Processor Global Control Register) */
+ {EPGCR, 0},
+ /* EPECR (Event Processor Event Control Registers) */
+ {EPECR0 + EPECR_STRIDE * 0, 0},
+ {EPECR0 + EPECR_STRIDE * 1, 0},
+ {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
+ {EPECR0 + EPECR_STRIDE * 3, 0x8084},
+ {EPECR0 + EPECR_STRIDE * 4, 0x2084},
+ {EPECR0 + EPECR_STRIDE * 5, 0x0804},
+ {EPECR0 + EPECR_STRIDE * 6, 0x8084},
+ {EPECR0 + EPECR_STRIDE * 7, 0x8084},
+ {EPECR0 + EPECR_STRIDE * 8, 0x6084},
+ {EPECR0 + EPECR_STRIDE * 9, 0x0884},
+ {EPECR0 + EPECR_STRIDE * 10, 0x4284},
+ {EPECR0 + EPECR_STRIDE * 11, 0x9084},
+ {EPECR0 + EPECR_STRIDE * 12, 0x8084},
+ {EPECR0 + EPECR_STRIDE * 13, 0x0884},
+ {EPECR0 + EPECR_STRIDE * 14, 0x0284},
+ {EPECR0 + EPECR_STRIDE * 15, 0x0004},
+ /*
+* EPEVTCR (Event Processor EVT Pin Control Registers)
+* SCU8 triger EVT2, and SCU11 triger EVT9
+*/
+ {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x8001},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
+ {EPEVTCR0 +
[PATCH 1/4] fsl: add EPU FSM configuration for deep sleep
T104x, T1024 and LS1021 of Freescale have a Finite State Machine (FSM)
to control the hardware precedure in deep sleep. Software will start
the FSM to enter deep sleep after finishing prepare work.
Then, when receiving a wakeup event, the FSM will restore the SoC to
work.
This driver configures and clears the FSM registers for deep sleep. Note
that the sequence of clearing the FSM registers does matter, should follow
the sequence mentioned in the reference manual.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
drivers/platform/Kconfig | 2 +
drivers/platform/Makefile| 1 +
drivers/platform/fsl/Kconfig | 11 ++
drivers/platform/fsl/Makefile| 5 +
drivers/platform/fsl/sleep_fsm.c | 263 +++
drivers/platform/fsl/sleep_fsm.h | 104
6 files changed, 386 insertions(+)
create mode 100644 drivers/platform/fsl/Kconfig
create mode 100644 drivers/platform/fsl/Makefile
create mode 100644 drivers/platform/fsl/sleep_fsm.c
create mode 100644 drivers/platform/fsl/sleep_fsm.h
diff --git a/drivers/platform/Kconfig b/drivers/platform/Kconfig
index 09fde58..85e3c95 100644
--- a/drivers/platform/Kconfig
+++ b/drivers/platform/Kconfig
@@ -6,3 +6,5 @@ source drivers/platform/goldfish/Kconfig
endif
source drivers/platform/chrome/Kconfig
+
+source drivers/platform/fsl/Kconfig
diff --git a/drivers/platform/Makefile b/drivers/platform/Makefile
index 3656b7b..37c6f72 100644
--- a/drivers/platform/Makefile
+++ b/drivers/platform/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_X86) += x86/
obj-$(CONFIG_OLPC) += olpc/
obj-$(CONFIG_GOLDFISH) += goldfish/
obj-$(CONFIG_CHROME_PLATFORMS) += chrome/
+obj-$(CONFIG_FSL_SOC) += fsl/
diff --git a/drivers/platform/fsl/Kconfig b/drivers/platform/fsl/Kconfig
new file mode 100644
index 000..a1ea46e
--- /dev/null
+++ b/drivers/platform/fsl/Kconfig
@@ -0,0 +1,11 @@
+#
+# Freescale Specific Power Management Drivers
+#
+
+config FSL_SLEEP_FSM
+ bool
+ help
+ This driver configures a hardware FSM (Finite State Machine) used in
deep sleep.
+ The FSM finishes clean-ups at the last stage of entering deep sleep,
and also
+ wakes up system when a wake up event happens. So far, T104x, T1024
and LS1021
+ need this.
diff --git a/drivers/platform/fsl/Makefile b/drivers/platform/fsl/Makefile
new file mode 100644
index 000..d99ca0e
--- /dev/null
+++ b/drivers/platform/fsl/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for linux/drivers/platform/fsl
+# Freescale Specific Power Management Drivers
+#
+obj-$(CONFIG_FSL_SLEEP_FSM)+= sleep_fsm.o
diff --git a/drivers/platform/fsl/sleep_fsm.c b/drivers/platform/fsl/sleep_fsm.c
new file mode 100644
index 000..0a0480a
--- /dev/null
+++ b/drivers/platform/fsl/sleep_fsm.c
@@ -0,0 +1,263 @@
+/*
+ * Freescale deep sleep FSM (finite-state machine) configuration
+ *
+ * Copyright 2014-2015 Freescale Semiconductor Inc.
+ *
+ * Author: Hongbo Zhang hongbo.zh...@freescale.com
+ * Chenhui Zhao chenhui.z...@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include linux/kernel.h
+#include linux/io.h
+#include linux/types.h
+
+#include sleep_fsm.h
+/*
+ * These values are from chip's reference manual. For example,
+ * the values for T1040 can be found in 8.4.3.8 Programming
+ * supporting deep sleep mode of Chapter 8 Run Control and
+ * Power Management (RCPM).
+ * The default value can be applied to T104x, T1024 and LS1021.
+ */
+struct fsm_reg_vals epu_default_val[] = {
+ /* EPGCR (Event Processor Global Control Register) */
+ {EPGCR, 0},
+ /* EPECR (Event Processor Event Control Registers) */
+ {EPECR0 + EPECR_STRIDE * 0, 0},
+ {EPECR0 + EPECR_STRIDE * 1, 0},
+ {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
+ {EPECR0 + EPECR_STRIDE * 3, 0x8084},
+ {EPECR0 + EPECR_STRIDE * 4, 0x2084},
+ {EPECR0 + EPECR_STRIDE * 5, 0x0804},
+ {EPECR0 + EPECR_STRIDE * 6, 0x8084},
+ {EPECR0 + EPECR_STRIDE * 7, 0x8084},
+ {EPECR0 + EPECR_STRIDE * 8, 0x6084},
+ {EPECR0 + EPECR_STRIDE * 9, 0x0884},
+ {EPECR0 + EPECR_STRIDE * 10, 0x4284},
+ {EPECR0 + EPECR_STRIDE * 11, 0x9084},
+ {EPECR0 + EPECR_STRIDE * 12, 0x8084},
+ {EPECR0 + EPECR_STRIDE * 13, 0x0884},
+ {EPECR0 + EPECR_STRIDE * 14, 0x0284},
+ {EPECR0 + EPECR_STRIDE * 15, 0x0004},
+ /*
+* EPEVTCR (Event Processor EVT Pin Control Registers)
+* SCU8 triger EVT2, and SCU11 triger EVT9
+*/
+ {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x8001},
+
