Re: [PATCH 1/5] x86/cpufeatures: Define feature bits to support mitigation of PSF

2021-04-09 Thread Saripalli, RK
On 4/9/2021 3:19 PM, Borislav Petkov wrote: > On Fri, Apr 09, 2021 at 02:45:23PM -0500, Saripalli, RK wrote: >> Yes, these options should be fine for now. >> Like you said, if we get the need to add prctl and seccomp, I can always do >> that later. >> >> What do you think auto should default

Re: [PATCH 1/5] x86/cpufeatures: Define feature bits to support mitigation of PSF

2021-04-09 Thread Borislav Petkov
On Fri, Apr 09, 2021 at 02:45:23PM -0500, Saripalli, RK wrote: > Yes, these options should be fine for now. > Like you said, if we get the need to add prctl and seccomp, I can always do > that later. > > What do you think auto should default to?. > In SSBD case, I believe auto defaults to prctl

Re: [PATCH 1/5] x86/cpufeatures: Define feature bits to support mitigation of PSF

2021-04-09 Thread Saripalli, RK
Boris, thank you. On 4/9/2021 2:39 PM, Borislav Petkov wrote: > On Fri, Apr 09, 2021 at 01:22:49PM -0500, Saripalli, RK wrote: >>> And I think you don't need this one either if we do a "light" controls >>> thing but lemme look at the rest first. > > Ok, and what I mean with "lite" version is

Re: [PATCH 1/5] x86/cpufeatures: Define feature bits to support mitigation of PSF

2021-04-09 Thread Borislav Petkov
On Fri, Apr 09, 2021 at 01:22:49PM -0500, Saripalli, RK wrote: > > And I think you don't need this one either if we do a "light" controls > > thing but lemme look at the rest first. Ok, and what I mean with "lite" version is something like this below which needs finishing and testing. Initially,

Re: [PATCH 1/5] x86/cpufeatures: Define feature bits to support mitigation of PSF

2021-04-09 Thread Saripalli, RK
On 4/9/2021 12:41 PM, Borislav Petkov wrote: > On Tue, Apr 06, 2021 at 10:50:00AM -0500, Ramakrishna Saripalli wrote: >> diff --git a/arch/x86/include/asm/cpufeatures.h >> b/arch/x86/include/asm/cpufeatures.h >> index cc96e26d69f7..21e7f8d0d7d9 100644 >> ---

Re: [PATCH 1/5] x86/cpufeatures: Define feature bits to support mitigation of PSF

2021-04-09 Thread Borislav Petkov
On Tue, Apr 06, 2021 at 10:50:00AM -0500, Ramakrishna Saripalli wrote: > diff --git a/arch/x86/include/asm/cpufeatures.h > b/arch/x86/include/asm/cpufeatures.h > index cc96e26d69f7..21e7f8d0d7d9 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@

[PATCH 1/5] x86/cpufeatures: Define feature bits to support mitigation of PSF

2021-04-06 Thread Ramakrishna Saripalli
From: Ramakrishna Saripalli Certain AMD processors feature a new technology called Predictive Store Forwarding (PSF). PSF is a micro-architectural optimization designed to improve the performance of code execution by predicting dependencies between loads and stores. Incorrect PSF predictions